Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Stubborn sets for reduced state generation
APN 90 Proceedings on Advances in Petri nets 1990
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
A generalized state assignment theory for transformations on signal transition graphs
Journal of VLSI Signal Processing Systems - Special issue: asynchronous circuit design for VLSI signal processing
Basic gate implementation of speed-independent circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
A design and validation system for asynchronous circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Synthesizing Petri nets from state-based models
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Decomposition and technology mapping of speed-independent circuits using Boolean relations
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Analysis of Petri Nets by Ordering Relations in Reduced Unfoldings
Formal Methods in System Design
Automatic synthesis of 3D asynchronous state machines
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Automatic gate-level synthesis of speed-independent circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Symbolic Model Checking
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Algorithms for Synthesis and Testing of Asynchronous Circuits
Algorithms for Synthesis and Testing of Asynchronous Circuits
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems
IEEE Transactions on Computers
Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets
Proceedings of the 16th International Conference on Application and Theory of Petri Nets
Using Partial Orders to Improve Automatic Verification Methods
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
General Conditions for the Decomposition of State-Holding Elements
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
A region-based theory for state assignment in speed-independent circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact two-level minimization of hazard-free logic with multiple-input changes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MOCSYN: multiobjective core-based single-chip system synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
CAD directions for high performance asynchronous circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Semi-modular Latch Chains for Asynchronous Circuit Design
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Symbolic model checking of Dual Transition Petri Nets
Proceedings of the tenth international symposium on Hardware/software codesign
Slack analysis in the system design loop
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
An optimal power algorithm for interface design of System-on-Chip
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
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Interfaces, by nature, are often asynchronous since they serve for connecting multiple distributed mod ules/agents without common clock. However, the most recent developments in the the ory of asynchronous design in the areas of specifications, mo dels, analysis, verification, synthesis, technology mapping, timing optimization and performanc e analysis are not widely known and r arely accepted by industry.The go al of this tutorial is to fill this gap and to present an overview of one p opular systematic design methodology for design of asynchronous interface controllers. This metho dology is based on using P etri nets (PN) a formal mo del that, from the engine ering standpoint, is a formalization of timing diagrams (waveforms) and from the system designer standpoint is a concurrent state machine, in which lo cal comp onents can perform indep endent or interdependent concurrent actions, changing their local states asynchronously. We will introduce this mo del informally b ased on a simple example: a VME-bus controller serving reads from a devic e to a bus and writes f rom the bus into the devic e.