Asynchronous interface specification, analysis and synthesis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Synthesis of asynchronous control circuits with automatically generated relative timing assumptions
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A structural encoding technique for the synthesis of asynchronous circuits
Fundamenta Informaticae - Application of concurrency to system design
Proceedings of the 41st annual Design Automation Conference
Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
State encoding of large asynchronous controllers
Proceedings of the 43rd annual Design Automation Conference
Getting rid of OR-joins and multiple start events in business process models
Enterprise Information Systems - Challenges and Solutions in Enterprise Computing - 11th International IEEE EDOC Conference (EDOC 2007)
A structural encoding technique for the synthesis of asynchronous circuits
Fundamenta Informaticae - Application of Concurrency to System Design
| Hi-index | 0.03 |
State assignment problems still need satisfactory solutions to make asynchronous circuit synthesis more practical. A well-known example of such a problem is that of complete state coding (CSC), which happens when a pair of different states in a specification has the same binary encoding. A standard way to approach state coding conflicts is to insert new state signals into the original specification in such a way that the original behavior remains intact. This paper proposes a method which improves over existing approaches by coupling generality, optimality, and efficiency. The method is based on the use of a class of “ground objects”, called regions, that play the role of a bridge between state-based specifications (transition systems, TS's) and event-based specifications (signal transition graphs, STG's), We need to deal with both types of specification because designers usually prefer a timing diagram-like notation, such as STG, while optimization and cost analysis work better at the state level. A region in a transition system is a set of states that corresponds to a place in an STG (or the underlying Petri net). Regions are tightly connected with a set of properties that are to be preserved across the state encoding process, namely, 1) trace equivalence between the original and the encoded specification, and 2) implementability as a speed-independent circuit. We will build on a theoretical body of work that has shown the significance of regions for such property-preserving transformations, and describe a set of algorithms aimed at efficiently solving the encoding problem. The algorithms have been implemented in a software tool called petrify. Unlike many existing tools, petrify represents the encoded specification as an STG. This significantly improves the readability of the result (compared to a state-based description in which concurrency is represented implicitly by interleaving), and allows the designer to be more closely involved in the synthesis process. The efficiency of the method is demonstrated on a number of “difficult” examples