Syntax-directed translation of concurrent programs into self-timed circuits
Proceedings of the fifth MIT conference on Advanced research in VLSI
Solving the state assignment problem for signal transition graphs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
Free choice Petri nets
The design of an asynchronous VHDL synthesizer
Proceedings of the conference on Design, automation and test in Europe
A Calculus of Communicating Systems
A Calculus of Communicating Systems
Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems
Signal Graphs: From Self-Timed to Timed Ones
International Workshop on Timed Petri Nets
Checking properties of nets using transformation
Advances in Petri Nets 1985, covers the 6th European Workshop on Applications and Theory in Petri Nets-selected papers
Towards Synthesis of Monotonic Asynchronous Circuits from Signal Transition Graphs
ACSD '01 Proceedings of the Second International Conference on Application of Concurrency to System Design
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Control Resynthesis for Control-Dominated Asynchronous Designs
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Automatic synthesis of gate-level timed circuits with choice
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Sequential optimization of asynchronous and synchronous finite-state machines: algorithms and tools
Sequential optimization of asynchronous and synchronous finite-state machines: algorithms and tools
Modular Design of Asynchronous Circuits Defined by Graphs
IEEE Transactions on Computers
A syntax-directed translation for the synthesis of delay-insensitive circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A region-based theory for state assignment in speed-independent circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Structural methods for the synthesis of speed-independent circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 41st annual Design Automation Conference
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'06)
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This paper presents a method for the automatic synthesis of asynchronous circuits from Petri net specifications. The method is based on a structural encoding of the system in such a way that a circuit implementation is always guaranteed. Moreover, a set of transformations is presented for the subclass of Free-Choice Petri nets that enables the exploration of different solutions. The set of transformations is derived from previous work on Petri net synthesis. Both the encoding technique and the set of transformations preserve the property of free-choiceness, thus enabling the use of structural methods for the synthesis of asynchronous circuits. Preliminary experimental results indicate that the quality of the circuits is comparable to that obtained by methods that require an exhaustive enumeration of the state space. This novel synthesis method opens the door to the synthesis of large control specifications generated from hardware description languages.