The design of an asynchronous VHDL synthesizer

  • Authors:
  • S.-Y. Tan;S. B. Furber;W.-F. Yen

  • Affiliations:
  • Department of Computer Science, University of Manchester, Manchester, M13 9PL, UK;Department of Computer Science, University of Manchester, Manchester, M13 9PL, UK;Department of Electronic Engineering, National Taipei University of Technology, T aipei, Taiwan, R.O.C.

  • Venue:
  • Proceedings of the conference on Design, automation and test in Europe
  • Year:
  • 1998

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Abstract

This paper presents a straightforward approach for synthesizing a standard VHDL description of an asynchronous circuit from a behavioral VHDL description. The asynchronous circuit style is based on "micropipelines", a style currently used to develop asynchronous microprocessors at Manchester University. The rules of partition and conversion which are used to implement the synthesizer are also described. The synthesizer greatly reduces the design time of a complex micropipeline circuit.