Communicating sequential processes
Communicating sequential processes
Communications of the ACM
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compiling the language Balsa to delay insensitive hardware
CHDL'97 Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems
Abstract modelling of asynchronous micropipeline systems using Rainbow
CHDL'97 Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems
ACM Computing Surveys (CSUR)
Communicating sequential processes
Communications of the ACM
The design of an asynchronous VHDL synthesizer
Proceedings of the conference on Design, automation and test in Europe
VLSI '93 Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration
Delay-Insensitive Circuits: An Algebraic Approach to their Design
CONCUR '90 Proceedings of the Theories of Concurrency: Unification and Extension
Modelling and Simulation of Asynchronous Systems Using the LARD Hardware Description Language
Proceedings of the 12th European Simulation Multiconference on Simulation - Past, Present and Future
Dynamic Logic in Four-Phase Micropipelines
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
AMULET2e: An Asynchronous Embedded Controller
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
SYNTHESIS OF SELF-TIMED VLSI CIRCUITS FROM GRAPH-THEORETIC SPECIFICATIONS
SYNTHESIS OF SELF-TIMED VLSI CIRCUITS FROM GRAPH-THEORETIC SPECIFICATIONS
A behavioral synthesis system for asynchronous circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Verification of delay insensitivity in bit-level pipelined dual-rail threshold logic adders
EHAC'08 Proceedings of the 7th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Algebraic model for the intercommunicating hardware components behaviour
ICCOMP'08 Proceedings of the 12th WSEAS international conference on Computers
The design of an asynchronous blocksorter
ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing
Synchronous design flow for globally asynchronous locally synchronous systems
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
The design of a simple asynchronous processor
MMACTEE'10 Proceedings of the 12th WSEAS international conference on Mathematical methods and computational techniques in electrical engineering
The design of sharing resources for asynchronous systems
MMACTEE'10 Proceedings of the 12th WSEAS international conference on Mathematical methods and computational techniques in electrical engineering
An evaluation for the design of asynchronous systems
WSEAS Transactions on Circuits and Systems
An optimization for the design of a simple asynchronous processor
WSEAS Transactions on Computers
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The asynchronous circuit style is based on micropipelines, a style used to develop asynchronous microprocessors at Manchester University. This paper has presented some engineering work on developing a micropipeline blocksorter. The work presented in this paper demonstrates that VHDL can be used to describe the behaviour of micropipelined systems. It also shows a comparison of 2-phase and 4-phase implementations in transistor count, speed, and energy. Though the nature of the work is mainly engineering, there are some significant new insights gained in the course of the work. In summary, a design environment for asynchronous circuits has been established based upon the micropipeline style and VHDL, a standard hardware description language.