A path-oriented approach for reducing hazards in asynchronous designs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Synthesis of concurrent system interface modules with automatic protocol conversion generation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Performance-driven synthesis of asynchronous controllers
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Decomposition methods for library binding of speed-independent asynchronous designs
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Hierarchical optimization of asynchronous circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Unifying synchronous/asynchronous state machine synthesis
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Automatic synthesis of 3D asynchronous state machines
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Exact two-level minimization of hazard-free logic with multiple-input changes
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Practical advances in asynchronous design and in asynchronous/synchronous interfaces
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Implementing asynchronous circuits using a conventional EDA tool-flow
Proceedings of the 39th annual Design Automation Conference
Distributed simulation of asynchronous hardware: the program driven synchronization protocol
Journal of Parallel and Distributed Computing
An FPGA for Implementing Asynchronous Circuits
IEEE Design & Test
Algorithms for the optimal state assignment of asynchronous state machines
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Proceedings of the 41st annual Design Automation Conference
Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An asynchronous low-power high-performance sequential decoder implemented with QDI templates
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Highly Scalable GALS Crossbar Using Token Ring Arbitration
IEEE Design & Test
A Case for Using Signal Transition Graphs for Analysing and Refining Genetic Networks
Electronic Notes in Theoretical Computer Science (ENTCS)
The design of an asynchronous blocksorter
ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing
A VHDL-based design methodology for asynchronous circuits
WSEAS Transactions on Circuits and Systems
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This thesis presents an approach for direct and efficient synthesis of self-timed (asynchronous) control circuits from formal specifications called Signal Transition Graphs (STGs). Control circuits synthesized from this graph model are speed-independent and capable of performing concurrent operation. The property of speed-independence means that the circuit operates correctly regardless of variations in delays of logic gates, thus implying that the circuit is hazard-free under any combination of gate delays. The capability of STGs for explicitly specifying concurrent operations internal to a control circuit is unique to this model, unlike other approaches based on Finite State Machines. STGs are a form of interpreted Petri nets, in which transitions in a net are interpreted as transitions of signals in a control circuit. While other synthesis approaches based on Petri nets have not been very successful, we have developed a number of analytical results which establish the equivalence between the static structure of nets (their syntax) and their underlying firing sequence semantics-an analytical approach called structure theory of Petri nets. This equivalence permits the characterization of the low-level properties of control circuits in terms of STG syntax: the properties of deadlock-free and hazard-preliminary STG specification of a control circuit can be modified into one which is live and persistent, from which a deadlock-free and hazard-free logic implementation can be derived mechanically. STGs allow efficient synthesis of control circuits by using a method of decomposition based on a graph-theoretic technique called contraction. Instead of implementing a logic circuit from a STG directly, it can first be decomposed into a number of contracted nets, one for each signal generated by the control circuit. A logic element can then be determined from each contracted net, and the composition of logic elements produces the final circuit implementation.