Communicating sequential processes
Communicating sequential processes
ACM Transactions on Programming Languages and Systems (TOPLAS)
Communications of the ACM
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Parallel discrete event simulation
Communications of the ACM - Special issue on simulation
The design of an asynchronous microprocessor
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
TITAC: Design of A Quasi-Delay-Insensitive Microprocessor
IEEE Design & Test
Parallel and distributed simulation of discrete event systems
Parallel and distributed simulation of discrete event systems
AMULET1: An Asynchronous ARM Microprocessor
IEEE Transactions on Computers
Dhrystone: a synthetic systems programming benchmark
Communications of the ACM
The development of the MU5 computer system
Communications of the ACM - Special issue on computer architecture
Time, clocks, and the ordering of events in a distributed system
Communications of the ACM
Asynchronous Digital Circuit Design
Asynchronous Digital Circuit Design
Introduction to VLSI Systems
Computer
The Counterflow Pipeline Processor Architecture
IEEE Design & Test
Delay-Insensitive Circuits: An Algebraic Approach to their Design
CONCUR '90 Proceedings of the Theories of Concurrency: Unification and Extension
Modelling and Simulation of Asynchronous Systems Using the LARD Hardware Description Language
Proceedings of the 12th European Simulation Multiconference on Simulation - Past, Present and Future
Hades-towards the design of an asynchronous superscalar processor
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
AMULET2e: An Asynchronous Embedded Controller
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
The architecture and system method of DDM1: A recursively structured Data Driven Machine
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Synthesis of Self-Timed Circuits by Program Transformation
Synthesis of Self-Timed Circuits by Program Transformation
SYNTHESIS OF SELF-TIMED VLSI CIRCUITS FROM GRAPH-THEORETIC SPECIFICATIONS
SYNTHESIS OF SELF-TIMED VLSI CIRCUITS FROM GRAPH-THEORETIC SPECIFICATIONS
The VLSI-programming language tangram and its translation into handshake circuits
EURO-DAC '91 Proceedings of the conference on European design automation
A formal approach to designing delay-insensitive circuits
Distributed Computing
Modelling SAMIPS: A Synthesisable Asynchronous MIPS Processor
ANSS '04 Proceedings of the 37th annual symposium on Simulation
A Framework for Distributed Simulation of Asynchronous Handshake Circuits
ANSS '06 Proceedings of the 39th annual Symposium on Simulation
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Synchronous VLSI design is approaching a critical point, with clock distribution becoming an increasingly costly and complicated issue and power consumption rapidly emerging as a major concern. Hence, recently, there has been a resurgence of interest in asynchronous digital design techniques which promise to liberate digital design from the inherent problems of synchronous systems. This activity has revealed a need for modelling and simulation techniques suitable for the asynchronous design style. The concurrent process algebra Communication Sequential Processes (CSP) and its executable counterpart, occam, are increasingly advocated as particularly suitable for this purpose. However, the parallel distributed semantics of CSP and occam introduce synchronization problems in the model. This paper presents the Program Driven Synchronization Protocol, which seeks to address causality and synchronization problems and enforce temporal coherency in distributed CSP/ occam models of asynchronous hardware systems.