Communications of the ACM
Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ARM System Architecture
Register Locking in an Asynchronous Microprocessor
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A Result Forwarding Mechanism for Asynchronous Pipelined Systems
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
AMULET2e: An Asynchronous Embedded Controller
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
The ARM9 Family - High Performance Microprocessors for Embedded Applications
ICCD '98 Proceedings of the International Conference on Computer Design
Practical advances in asynchronous design and in asynchronous/synchronous interfaces
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A New Control Circuit for Asynchronous Micropipelines
IEEE Transactions on Computers
An adaptive serial-parallel CAM architecture for low-power cache blocks
Proceedings of the 2002 international symposium on Low power electronics and design
Distributed simulation of asynchronous hardware: the program driven synchronization protocol
Journal of Parallel and Distributed Computing
Typing Assembly Programs with Explicit Forwarding
TACS '01 Proceedings of the 4th International Symposium on Theoretical Aspects of Computer Software
A Coarse-Grain Phased Logic CPU
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Adaptive Pipeline Structures fo Speculation Control
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
A Coarse-Grain Phased Logic CPU
IEEE Transactions on Computers
Simulation of gate circuits in the algebra of transients
CIAA'02 Proceedings of the 7th international conference on Implementation and application of automata
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AMULET3 is the third fully asynchronous implementation of the ARM architecture designed at the University of Manchester. It implements the most recent version of the ARM architecture (v4T), including the Thumb instruction set. Significant architectural changes from its predecessors help achieve higher performance without sacrificing the advantages of asynchronous design and some new power-saving features have been incorporated.This paper outlines the AMULET3 microprocessor core, highlighting where this design differs from its predecessors. Most notable among the changes are the use of a Harvard architecture to increase memory bandwidth and the inclusion of a reorder buffer to handle data forwarding and memory faults.