Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Way-predicting set-associative cache for high performance and low energy consumption
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
L1 data cache decomposition for energy efficiency
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
SH3: High Code Density, Low Power
IEEE Micro
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Predictive sequential associative cache
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
A hybrid adiabatic content addressable memory for ultra low-power applications
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A way-halting cache for low-energy high-performance systems
Proceedings of the 2004 international symposium on Low power electronics and design
A way-halting cache for low-energy high-performance systems
ACM Transactions on Architecture and Code Optimization (TACO)
Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches
Proceedings of the 33rd annual international symposium on Computer Architecture
Improve CAM power efficiency using decoupled match line scheme
Proceedings of the conference on Design, automation and test in Europe
Reducing cache misses through programmable decoders
ACM Transactions on Architecture and Code Optimization (TACO)
Optimizing CAM-based instruction cache designs for low-power embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
Hybrid-type CAM design for both power and performance efficiency
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Transactions on High-Performance Embedded Architectures and Compilers II
Journal of Parallel and Distributed Computing
Don't-care gating (DCG) TCAM design used in network routing table
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A CAM with mixed serial-parallel comparison for use in low energy caches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Energy and throughput efficient transactional memory for embedded multicore systems
HiPEAC'10 Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers
A tagless cache design for power saving in embedded systems
The Journal of Supercomputing
An error tolerant CAM with nand match-line organization
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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There is an on-going debate about which consumes less energy: a RAM-tagged associative cache with an intelligent order of accessing its tags and ways (e.g. way prediction), or a CAM-tagged high associativity cache. If a CAM search can consume less than twice the energy of reading a tag RAM, it would probably be the preferred option for low-power applications. Based on memory traces --- which usually cause tag mismatch within the lower four bits --- a new serial CAM organisation is proposed which consumes just 45% more than a single tag RAM read and is only 25% slower than the conventional, parallel CAM. Furthermore, it can optionally be operated as a parallel CAM, at no speed penalty, and still reduce energy consumption.