Reducing TLB power requirements
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
An adaptive serial-parallel CAM architecture for low-power cache blocks
Proceedings of the 2002 international symposium on Low power electronics and design
Design of novel CAM core cell structures for an efficient implementation of low power BCAM system
Proceedings of the 19th ACM Great Lakes symposium on VLSI
A high-performance and energy-efficient TCAM design for IP-address lookup
IEEE Transactions on Circuits and Systems II: Express Briefs
Don't-care gating (DCG) TCAM design used in network routing table
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Content addressable memory (CAM) is widely used in many applications that require fast table lookup. Due to the parallel comparison feature and high frequency of lookup, however, the power consumption of CAM is usually significant. In this paper we propose a decoupled match line scheme which combines the performance advantage of the traditional NOR-type CAM and the power efficiency of the traditional NAND-type CAM. In our design, a CAM word is divided into two segments, and then all the CAM cells are decoupled from the match line. By minimizing both the match line capacitances and switching activities, our design can largely reduce the CAM power dissipated in search operations. The results measured from the fabricated chip show that without any performance penalty our design can reduce the search energy consumption of the CAM by 89% compared to the traditional NOR-type CAM design.