A case for two-way skewed-associative caches
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
SODA '90 Proceedings of the first annual ACM-SIAM symposium on Discrete algorithms
A Low-Power CAM Design for LZ Data Compression
IEEE Transactions on Computers
An adaptive serial-parallel CAM architecture for low-power cache blocks
Proceedings of the 2002 international symposium on Low power electronics and design
A hybrid adiabatic content addressable memory for ultra low-power applications
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Use of selective precharge for low-power on the match lines of content-addressable memories
MTDT '97 Proceedings of the 1997 IEEE International Workshop on Memory Technology, Design and Testing
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Content addressable memories (CAMs) are commonly used in applications requiring high speed access to some data set. This technology allows data items to be accessed in constant time based on content rather than on address. Unfortunately this technology has several drawbacks: it occupies more die area per bit, dissipates more power, and has higher latency. Recently, an efficient architecture based on a parallel hashing has been proposed as an alternative to CAM technology. In the present paper, we go a step further by backing preliminary simulation results of this proposed architecture by a complete analytical model. The insertion operations applied on the proposed architecture can be modeled with the balls and urns problem. We also propose a method to identify optimal configuration parameters in order to start designing efficiently. Finally, a VLSI implementation and optimizations of the proposed architecture are presented in order to obtain a more thorough understanding of how it could compare to commercial CAMs. Because of its simple design and of the widely spread use of the required tools, this new architecture offers a very appealing alternative to CAM technology.