Cache design of a sub-micron CMOS system/370
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Inexpensive implementations of set-associativity
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Energy optimization of multi-level processor cache architectures
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Cache design trade-offs for power and performance optimization: a case study
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
The filter cache: an energy efficient memory structure
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
SH3: High Code Density, Low Power
IEEE Micro
The MIPS R10000 Superscalar Microprocessor
IEEE Micro
Predictive sequential associative cache
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
Energy-driven integrated hardware-software optimizations using SimplePower
Proceedings of the 27th annual international symposium on Computer architecture
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Reducing cache engery through dual voltage supply
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
L1 data cache decomposition for energy efficiency
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Power-aware partitioned cache architectures
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Energy-efficient instruction cache using page-based placement
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Sentry tag: an efficient filter scheme for low power cache
CRPIT '02 Proceedings of the seventh Asia-Pacific conference on Computer systems architecture
Reducing set-associative cache energy via way-prediction and selective direct-mapping
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Fine-grain CAM-tag cache resizing using miss tags
Proceedings of the 2002 international symposium on Low power electronics and design
An adaptive serial-parallel CAM architecture for low-power cache blocks
Proceedings of the 2002 international symposium on Low power electronics and design
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Energy-performance trade-offs for spatial access methods on memory-resident data
The VLDB Journal — The International Journal on Very Large Data Bases
Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework
IEEE Transactions on Computers
Partitioned instruction cache architecture for energy efficiency
ACM Transactions on Embedded Computing Systems (TECS)
Integrated I-cache Way Predictor and Branch Target Buffer to Reduce Energy Consumption
ISHPC '02 Proceedings of the 4th International Symposium on High Performance Computing
A Holistic Approach to System Level Energy Optimization
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Energy frugal tags in reprogrammable I-caches for application-specific embedded processors
Proceedings of the tenth international symposium on Hardware/software codesign
Generating physical addresses directly for saving instruction TLB energy
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
A highly configurable cache architecture for embedded systems
Proceedings of the 30th annual international symposium on Computer architecture
Reducing data cache energy consumption via cached load/store queue
Proceedings of the 2003 international symposium on Low power electronics and design
On load latency in low-power caches
Proceedings of the 2003 international symposium on Low power electronics and design
Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Design and analysis of low-power cache using two-level filter scheme
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An energy efficient cache memory architecture for embedded systems
Proceedings of the 2004 ACM symposium on Applied computing
Low Static-Power Frequent-Value Data Caches
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Value-Conscious Cache: Simple Technique for Reducing Cache Access Power
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Dynamic techniques to reduce memory traffic in embedded systems
Proceedings of the 1st conference on Computing frontiers
Coupling compiler-enabled and conventional memory accessing for energy efficiency
ACM Transactions on Computer Systems (TOCS)
A self-tuning cache architecture for embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Location cache: a low-power L2 cache system
Proceedings of the 2004 international symposium on Low power electronics and design
A VLIW low power Java processor for embedded applications
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A leakage-energy-reduction technique for highly-associative caches in embedded systems
MEDEA '03 Proceedings of the 2003 workshop on MEmory performance: DEaling with Applications , systems and architecture
Using a serial cache for energy efficient instruction fetching
Journal of Systems Architecture: the EUROMICRO Journal
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Energy-security tradeoff in a secure cache architecture against buffer overflow attacks
ACM SIGARCH Computer Architecture News - Special issue: Workshop on architectural support for security and anti-virus (WASSA)
Optimizing instruction TLB energy using software and hardware techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A way-halting cache for low-energy high-performance systems
ACM Transactions on Architecture and Code Optimization (TACO)
IATAC: a smart predictor to turn-off L2 cache lines
ACM Transactions on Architecture and Code Optimization (TACO)
A highly configurable cache for low energy embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Synonymous address compaction for energy reduction in data TLB
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
RECAST: Boosting Tag Line Buffer Coverage in Low-Power High-Level Caches "for Free"
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Reducing energy of virtual cache synonym lookup using bloom filters
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Scientific applications vs. SPEC-FP: a comparison of program behavior
Proceedings of the 20th annual international conference on Supercomputing
Proceedings of the 20th annual international conference on Supercomputing
A cache design for high performance embedded systems
Journal of Embedded Computing - Cache exploitation in embedded systems
Reducing non-deterministic loads in low-power caches via early cache set resolution
Microprocessors & Microsystems
Compiler-managed partitioned data caches for low power
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Reducing cache energy consumption by tag encoding in embedded processors
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Dynamic tag reduction for low-power caches in embedded systems with virtual memory
International Journal of Parallel Programming
ILP-Based energy minimization techniques for banked memories
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Word-interleaved cache: an energy efficient data cache architecture
Proceedings of the 13th international symposium on Low power electronics and design
Instruction cache energy saving through compiler way-placement
Proceedings of the conference on Design, automation and test in Europe
Improved Way Prediction Policy for Low-Energy Instruction Caches
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Optimizing CAM-based instruction cache designs for low-power embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
A novel cache architecture with enhanced performance and security
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Reconfigurable energy efficient near threshold cache architectures
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches
Transactions on High-Performance Embedded Architectures and Compilers II
Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems
Transactions on High-Performance Embedded Architectures and Compilers II
Less reused filter: improving l2 cache performance via filtering less reused lines
Proceedings of the 23rd international conference on Supercomputing
Way-tagged cache: an energy-efficient L2 cache architecture under write-through policy
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Way guard: a segmented counting bloom filter approach to reducing energy for set-associative caches
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
The Design and Evaluation of a Selective Way Based Trace Cache
APPT '09 Proceedings of the 8th International Symposium on Advanced Parallel Processing Technologies
Efficient line buffer instruction cache scheme with prefetch
Proceedings of the 2nd International Conference on Interaction Sciences: Information Technology, Culture and Human
An hybrid eDRAM/SRAM macrocell to implement first-level data caches
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Leveraging high performance data cache techniques to save power in embedded systems
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
Applying decay to reduce dynamic power in set-associative caches
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
Early-stage definition of LPX: a low power issue-execute processor
PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems
PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems
Using a way cache to improve performance of set-associative caches
ISHPC'05/ALPS'06 Proceedings of the 6th international symposium on high-performance computing and 1st international conference on Advanced low power systems
WHOLE: a low energy I-cache with separate way history
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Dynamic, non-linear cache architecture for power-sensitive mobile processors
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Location cache design and performance analysis for chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A CAM with mixed serial-parallel comparison for use in low energy caches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Microprocessors & Microsystems
Energy efficient united l2 cache design with instruction/data filter scheme
APPT'05 Proceedings of the 6th international conference on Advanced Parallel Processing Technologies
Selective word reading for high performance and low power processor
Proceedings of the 2011 ACM Symposium on Research in Applied Computation
Energy-Effective instruction fetch unit for wide issue processors
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
A tagless cache design for power saving in embedded systems
The Journal of Supercomputing
Euro-Par'12 Proceedings of the 18th international conference on Parallel Processing
Low power cache architectures with hybrid approach of filtering unnecessary way accesses
Proceedings of the 2013 International Workshop on Programming Models and Applications for Multicores and Manycores
Towards a performance- and energy-efficient data filter cache
Proceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems
MALEC: a multiple access low energy cache
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An energy-efficient L2 cache architecture using way tag information under write-through policy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Buffered Dual-Access-Mode Scheme Designed for Low-Power Highly-Associative Caches
International Journal of Embedded and Real-Time Communication Systems
Application-aware adaptive cache architecture for power-sensitive mobile processors
ACM Transactions on Embedded Computing Systems (TECS)
Designing a practical data filter cache to improve both energy efficiency and performance
ACM Transactions on Architecture and Code Optimization (TACO)
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