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Communications of the ACM
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Proceedings of the 38th annual international symposium on Computer architecture
Energy efficient united l2 cache design with instruction/data filter scheme
APPT'05 Proceedings of the 6th international conference on Advanced Parallel Processing Technologies
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Power has been a big issue in processor design for several years. As caches account for more and more CPU die area and power, this paper presents using filtering unnecessary way accesses to reduce dynamic power consumption of unified L2 cache shared by instruction and data. Our methods include using Invalid Filter, which could eliminate accesses to cache ways contained invalid blocks, and I/D Filter, which could eliminate accesses to cache ways contained instruction/data access type mismatch blocks, and Tag-2 Filter, which could eliminate accesses to cache ways contained tag lowest 2 bits mismatch blocks. Since the methods reducing the activities happened in cache architecture, dynamical CPU power could be significantly decreased. In the paper, we also propose combining the above methods together(Invalid+I/D+Tag-2 Filter), which is called Way-Filtering Cache, in an attempt to achieve better power saving results. Our evaluations show that, we could obtain 19.6%-47.8% (which is on average 34.3%)improvement on a 64K-4way cache and 19.6%-55.2%(which is on average 39.2%) improvement on a 128k-8way cache comparing to Invalid+I/D Filter, and 6.1%-27.7%(which is on average 16.6%) improvement on a 64K-4way cache and 6.9%-44.4%(which is on average 25.0%) improvement on a 128k-8way cache comparing to Invalid+Tag-2 Filter, respectively. Also, comparing to Tag-Data caches, which is popular used in less-latency-sensitive caches(e.g. unified L2 or Shared Last-LevelCache), our Way-Filtering cache could get 18.3%-29.2%(which is on average 23.1%) improvement on 64K-4way cache, and 27.2% to 50.1%(which is on average 41.1%) improvement on 128K-8way cache.