On the inclusion properties for multi-level cache hierarchies
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
A model for estimating trace-sample miss ratios
SIGMETRICS '91 Proceedings of the 1991 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Operating systems
A comparison of dynamic branch predictors that use two levels of branch history
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Circuit implementation of a 300-MHz 64-bit second-generation CMOS Alpha CPU
Digital Technical Journal - Special 10th anniversary issue
Dynamic self-invalidation: reducing coherence overhead in shared-memory multiprocessors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Reducing TLB and memory overhead using online superpage promotion
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Analytical energy dissipation models for low-power caches
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Designing high bandwidth on-chip caches
Proceedings of the 24th annual international symposium on Computer architecture
ProfileMe: hardware support for instruction-level profiling on out-of-order processors
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Empirical studies of competitve spinning for a shared-memory multiprocessor
SOSP '91 Proceedings of the thirteenth ACM symposium on Operating systems principles
Capturing dynamic memory reference behavior with adaptive cache topology
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
IEEE Transactions on Computers
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
A fully associative software-managed cache design
Proceedings of the 27th annual international symposium on Computer architecture
Selective, accurate, and timely self-invalidation using last-touch prediction
Proceedings of the 27th annual international symposium on Computer architecture
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Near-Optimal Parallel Prefetching and Caching
SIAM Journal on Computing
Eager writeback - a technique for improving bandwidth utilization
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
A static power model for architects
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Performance analysis using the MIPS R10000 performance counters
Supercomputing '96 Proceedings of the 1996 ACM/IEEE conference on Supercomputing
Design Challenges of Technology Scaling
IEEE Micro
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Improving Replacement Decisions in Set-Associative Caches TITLE2:
Improving Replacement Decisions in Set-Associative Caches TITLE2:
Establishing a tight bound on task interference in embedded system instruction caches
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Dynamic fine-grain leakage reduction using leakage-biased bitlines
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Timekeeping in the memory system: predicting and optimizing memory behavior
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Reducing set-associative cache energy via way-prediction and selective direct-mapping
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Managing leakage for transient data: decay and quasi-static 4T memory cells
Proceedings of the 2002 international symposium on Low power electronics and design
Fine-grain CAM-tag cache resizing using miss tags
Proceedings of the 2002 international symposium on Low power electronics and design
Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors
Proceedings of the 2002 international symposium on Low power electronics and design
An integrated approach to reducing power dissipation in memory hierarchies
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Tuning garbage collection for reducing memory system energy in an embedded java environment
ACM Transactions on Embedded Computing Systems (TECS)
Partitioned instruction cache architecture for energy efficiency
ACM Transactions on Embedded Computing Systems (TECS)
HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
Leakage Energy Management in Cache Hierarchies
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
Enhancing Compiler Techniques for Memory Energy Optimizations
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Adaptive Garbage Collection for Battery-Operated Environments
Proceedings of the 2nd Java Virtual Machine Research and Technology Symposium
Compiler-directed instruction cache leakage optimization
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Managing static leakage energy in microprocessor functional units
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Xtream-Fit: an energy-delay efficient data memory subsystem for embedded media processing
Proceedings of the 40th annual Design Automation Conference
Adapting instruction level parallelism for optimizing leakage in VLIW architectures
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
A compiler approach for reducing data cache energy
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Adaptive mode control: A static-power-efficient cache design
ACM Transactions on Embedded Computing Systems (TECS)
A forward body-biased low-leakage SRAM cache: device and architecture considerations
Proceedings of the 2003 international symposium on Low power electronics and design
On load latency in low-power caches
Proceedings of the 2003 international symposium on Low power electronics and design
Exploiting program hotspots and code sequentiality for instruction cache leakage management
Proceedings of the 2003 international symposium on Low power electronics and design
Static energy reduction techniques for microprocessor caches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Tracking object life cycle for leakage energy optimization
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Performance, energy, and reliability tradeoffs in replicating hot cache lines
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Low-leakage asymmetric-cell SRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy management of virtual memory on diskless devices
Compilers and operating systems for low power
Low Static-Power Frequent-Value Data Caches
Proceedings of the conference on Design, automation and test in Europe - Volume 1
State-Preserving vs. Non-State-Preserving Leakage Control in Caches
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Reducing instruction cache energy consumption using a compiler-based strategy
ACM Transactions on Architecture and Code Optimization (TACO)
Circuit and microarchitectural techniques for reducing cache leakage power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A self-tuning cache architecture for embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Back-end assignment schemes for clustered multithreaded processors
Proceedings of the 18th annual international conference on Supercomputing
LRU-SEQ: A Novel Replacement Policy for Transition Energy Reduction in Instruction Caches
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Implementing branch-predictor decay using quasi-static memory cells
ACM Transactions on Architecture and Code Optimization (TACO)
Microarchitectural techniques for power gating of execution units
Proceedings of the 2004 international symposium on Low power electronics and design
Single-vDD and single-vT super-drowsy techniques for low-leakage high-performance instruction caches
Proceedings of the 2004 international symposium on Low power electronics and design
4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors
Proceedings of the 2004 international symposium on Low power electronics and design
HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction
Proceedings of the 2004 international symposium on Low power electronics and design
Soft error and energy consumption interactions: a data cache perspective
Proceedings of the 2004 international symposium on Low power electronics and design
Profile-based adaptation for cache decay
ACM Transactions on Architecture and Code Optimization (TACO)
Static next sub-bank prediction for drowsy instruction cache
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Optimizing Array-Intensive Applications for On-Chip Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
ChipLock: support for secure microarchitectures
ACM SIGARCH Computer Architecture News - Special issue: Workshop on architectural support for security and anti-virus (WASSA)
Energy management in software-controlled multi-level memory hierarchies
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
IATAC: a smart predictor to turn-off L2 cache lines
ACM Transactions on Architecture and Code Optimization (TACO)
Accelerated warmup for sampled microarchitecture simulation
ACM Transactions on Architecture and Code Optimization (TACO)
Skewed caches from a low-power perspective
Proceedings of the 2nd conference on Computing frontiers
Controlling leakage power with the replacement policy in slumberous caches
Proceedings of the 2nd conference on Computing frontiers
Exploiting temporal locality in drowsy cache policies
Proceedings of the 2nd conference on Computing frontiers
Drowsy region-based caches: minimizing both dynamic and static power dissipation
Proceedings of the 2nd conference on Computing frontiers
A highly configurable cache for low energy embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Increasing Data TLB Resilience to Transient Errors
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
A simple mechanism to adapt leakage-control policies to temperature
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Snug set-associative caches: reducing leakage power while improving performance
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
An efficient direct mapped instruction cache for application-specific embedded systems
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Reducing data cache leakage energy using a compiler-based approach
ACM Transactions on Embedded Computing Systems (TECS)
Exploring the limits of leakage power reduction in caches
ACM Transactions on Architecture and Code Optimization (TACO)
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
Counter-Based Cache Replacement Algorithms
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Optimizing the Thermal Behavior of Subarrayed Data Caches
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency
IEEE Transactions on Computers
Power reduction techniques for microprocessor systems
ACM Computing Surveys (CSUR)
Banked scratch-pad memory management for reducing leakage energy consumption
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Compiler-directed high-level energy estimation and optimization
ACM Transactions on Embedded Computing Systems (TECS)
Energy-aware computation duplication for improving reliability in embedded chip multiprocessors
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Prefetching-aware cache line turnoff for saving leakage energy
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Low-leakage robust SRAM cell design for sub-100nm technologies
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Studying interactions between prefetching and cache line turnoff
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Compilers for leakage power reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power density minimization for highly-associative caches in embedded processors
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
STV-Cache: a leakage energy-efficient architecture for data caches
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Activity clustering for leakage management in SPMs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Area-efficient error protection for caches
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Microarchitectural floorplanning under performance and thermal tradeoff
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Reducing dynamic and leakage energy in VLIW architectures
ACM Transactions on Embedded Computing Systems (TECS)
Memory management challenges in the power-aware computing era
Proceedings of the 5th international symposium on Memory management
Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches
Proceedings of the 33rd annual international symposium on Computer Architecture
A case for asymmetric-cell cache memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Systematic temperature sensor allocation and placement for microprocessors
Proceedings of the 43rd annual Design Automation Conference
Leakage power reduction of embedded memories on FPGAs through location assignment
Proceedings of the 43rd annual Design Automation Conference
Microarchitecture-level leakage reduction with data retention
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Process variation aware cache leakage management
Proceedings of the 2006 international symposium on Low power electronics and design
Investigating cache energy and latency break-even points in high performance processors
MEDEA '06 Proceedings of the 2006 workshop on MEmory performance: DEaling with Applications, systems and architectures
Evaluating instruction cache vulnerability to transient errors
MEDEA '06 Proceedings of the 2006 workshop on MEmory performance: DEaling with Applications, systems and architectures
Power efficient branch prediction through early identification of branch addresses
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Compiler-assisted leakage energy optimization for clustered VLIW architectures
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
Proceedings of the 20th annual international conference on Supercomputing
ACM Transactions on Computer Systems (TOCS)
ACM Transactions on Architecture and Code Optimization (TACO)
Exploiting loop behavior for data cache leakage reduction
Journal of Embedded Computing - Cache exploitation in embedded systems
Reducing branch predictor leakage energy by exploiting loops
ACM Transactions on Embedded Computing Systems (TECS) - SPECIAL ISSUE SCOPES 2005
Unified microprocessor core storage
Proceedings of the 4th international conference on Computing frontiers
Adaptive insertion policies for high performance caching
Proceedings of the 34th annual international symposium on Computer architecture
Compiler-Directed Variable Latency Aware SPM Management to CopeWith Timing Problems
Proceedings of the International Symposium on Code Generation and Optimization
Modeling and improving data cache reliability: 1
Proceedings of the 2007 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Architectural leakage-aware management of partitioned scratchpad memories
Proceedings of the conference on Design, automation and test in Europe
Locality-driven architectural cache sub-banking for leakage energy reduction
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Cache leakage control mechanism for hard real-time systems
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Integration, the VLSI Journal
Reducing leakage in power-saving capable caches for embedded systems by using a filter cache
MEDEA '07 Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture
A power-aware shared cache mechanism based on locality assessment of memory reference for CMPs
MEDEA '07 Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture
Investigating cache energy and latency break-even points in high performance processors
ACM SIGARCH Computer Architecture News
Evaluating instruction cache vulnerability to transient errors
ACM SIGARCH Computer Architecture News
Reducing cache misses through programmable decoders
ACM Transactions on Architecture and Code Optimization (TACO)
On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance
IEEE Transactions on Computers
Leakage energy reduction in cache memory by data compression
ACM SIGARCH Computer Architecture News - Special issue: ALPS '07---advanced low power systems
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells
Proceedings of the 18th ACM Great Lakes symposium on VLSI
ILP-Based energy minimization techniques for banked memories
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Compiler-guided next sub-bank prediction for reducing instruction cache leakage energy
Journal of Embedded Computing - Embeded Processors and Systems: Architectural Issues and Solutions for Emerging Applications
Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation
Proceedings of the 13th international symposium on Low power electronics and design
Word-interleaved cache: an energy efficient data cache architecture
Proceedings of the 13th international symposium on Low power electronics and design
Instruction cache energy saving through compiler way-placement
Proceedings of the conference on Design, automation and test in Europe
Improved Way Prediction Policy for Low-Energy Instruction Caches
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Capturing and optimizing the interactions between prefetching and cache line turnoff
Microprocessors & Microsystems
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Case study of reliability-aware and low-power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Specializing Cache Structures for High Performance and Energy Conservation in Embedded Systems
Transactions on High-Performance Embedded Architectures and Compilers I
Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture
Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Evaluating the effects of cache redundancy on profit
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Cache Controller Design on Ultra Low Leakage Embedded Processors
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches
Transactions on High-Performance Embedded Architectures and Compilers II
Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems
Transactions on High-Performance Embedded Architectures and Compilers II
Hardware-compiler co-design for adjustable data power savings
Microprocessors & Microsystems
An architectural co-synthesis algorithm for energy-aware Network-on-Chip design
Journal of Systems Architecture: the EUROMICRO Journal
Techniques for leakage energy reduction in deep submicrometer cache memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches
Proceedings of the 36th annual international symposium on Computer architecture
Enabling ultra low voltage system operation by tolerating on-chip cache failures
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
A DVS-based pipelined reconfigurable instruction memory
Proceedings of the 46th Annual Design Automation Conference
Flexible cache error protection using an ECC FIFO
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
Using data compression for increasing memory system utilization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Results on leakage power management in scratchpad-based embedded systems
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
Reducing peak power with a table-driven adaptive processor core
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
An hybrid eDRAM/SRAM macrocell to implement first-level data caches
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Algorithms for memory hierarchies: advanced lectures
Algorithms for memory hierarchies: advanced lectures
Leveraging high performance data cache techniques to save power in embedded systems
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
Applying decay to reduce dynamic power in set-associative caches
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
Reuse distance based cache leakage control
HiPC'07 Proceedings of the 14th international conference on High performance computing
Aging effects of leakage optimizations for caches
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Integrated CPU cache power management in multiple clock domain processors
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
Where replacement algorithms fail: a thorough analysis
Proceedings of the 7th ACM international conference on Computing frontiers
Proceedings of the 7th ACM international conference on Computing frontiers
An utilization driven framework for energy efficient caches
HiPC'08 Proceedings of the 15th international conference on High performance computing
Compiler-directed leakage reduction in embedded microprocessors
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Instruction-based reuse-distance prediction for effective cache management
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
High performance cache replacement using re-reference interval prediction (RRIP)
Proceedings of the 37th annual international symposium on Computer architecture
Modeling soft errors for data caches and alleviating their effects on data reliability
Microprocessors & Microsystems
Replica victim caching to improve cache reliability against transient errors
International Journal of High Performance Systems Architecture
Replication-aware leakage management in chip multiprocessors with private L2 cache
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Dynamic indexing: concurrent leakage and aging optimization for caches
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Leakage-efficient design of value predictors through state and non-state preserving techniques
The Journal of Supercomputing
Leakage-aware multiprocessor scheduling for low power
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
SRAM leakage reduction by row/column redundancy under random within-die delay variation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adaptive timekeeping replacement: Fine-grained capacity management for shared CMP caches
ACM Transactions on Architecture and Code Optimization (TACO)
Low Power Design for a Multi-core Multi-thread Microprocessor
GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing
Compiler-guided leakage optimization for banked scratch-pad memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Quantitative analysis and optimization techniques for on-chip cache leakage power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Soft errors issues in low-power caches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Saving register-file static power by monitoring instruction sequence in ROB
Journal of Systems Architecture: the EUROMICRO Journal
Power-aware dynamic cache partitioning for CMPs
Transactions on high-performance embedded architectures and compilers III
Transactions on high-performance embedded architectures and compilers III
A framework for correction of multi-bit soft errors in L2 caches based on redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coordinating processor and main memory for efficientserver power control
Proceedings of the international conference on Supercomputing
Eliminating energy of same-content-cell-columns of on-chip SRAM arrays
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Power gating strategies on GPUs
ACM Transactions on Architecture and Code Optimization (TACO)
Dynamic access distance driven cache replacement
ACM Transactions on Architecture and Code Optimization (TACO)
Power management of hybrid DRAM/PRAM-based main memory
Proceedings of the 48th Design Automation Conference
Proceedings of the 48th Design Automation Conference
A QoS Guaranteed Cache Design for Environment Friendly Computing
GREENCOM '11 Proceedings of the 2011 IEEE/ACM International Conference on Green Computing and Communications
Using branch prediction information for near-optimal i-cache leakage
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Dynamic dictionary-based data compression for level-1 caches
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
Do trace cache, value prediction and prefetching improve SMT throughput?
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
Saving register-file leakage power by monitoring instruction sequence in ROB
EUC'06 Proceedings of the 2006 international conference on Emerging Directions in Embedded and Ubiquitous Computing
Compiler analysis and supports for leakage power reduction on microprocessors
LCPC'02 Proceedings of the 15th international conference on Languages and Compilers for Parallel Computing
Residue cache: a low-energy low-area L2 cache architecture via compression and partial hits
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
SHiP: signature-based hit predictor for high performance caching
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Exploring the potential of architecture-level power optimizations
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
Hot-and-Cold: using criticality in the design of energy-efficient caches
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
An innovative instruction cache for embedded processors
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Efficient architectural support for secure bus-based shared memory multiprocessor
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Cache leakage management for multi-programming workloads
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Reducing execution unit leakage power in embedded processors
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Preventing denial-of-service attacks in shared CMP caches
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Recent thermal management techniques for microprocessors
ACM Computing Surveys (CSUR)
Link-time optimization for power efficiency in a tagless instruction cache
CGO '11 Proceedings of the 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization
A novel power-gating scheme utilizing data retentiveness on caches
Proceedings of the great lakes symposium on VLSI
Compiler-assisted energy optimization for clustered VLIW processors
Journal of Parallel and Distributed Computing
NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems
Journal of Electronic Testing: Theory and Applications
Complexity-effective multicore coherence
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
Leakage energy reduction in cache memory by software self-invalidation
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
Exploiting reuse locality on inclusive shared last-level caches
ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers
Euro-Par'12 Proceedings of the 18th international conference on Parallel Processing
Low power cache architectures with hybrid approach of filtering unnecessary way accesses
Proceedings of the 2013 International Workshop on Programming Models and Applications for Multicores and Manycores
Power devil: tool for power gating strategy selection
Proceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems
A survey on cache tuning from a power/energy perspective
ACM Computing Surveys (CSUR)
Combating NBTI-induced aging in data caches
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes
Proceedings of the Conference on Design, Automation and Test in Europe
D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory
Proceedings of the Conference on Design, Automation and Test in Europe
Enhancing NBTI recovery in SRAM arrays through recovery boosting
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamically reconfigurable hybrid cache: an energy-efficient last-level cache design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
DESC: energy-efficient data exchange using synchronized counters
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
The reuse cache: downsizing the shared last-level cache
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
ARGO: aging-aware GPGPU register file allocation
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
An effectiveness-based adaptive cache replacement policy
Microprocessors & Microsystems
Hi-index | 0.01 |
Power dissipation is increasingly important in CPUs ranging from those intended for mobile use, all the way up to high-performance processors for high-end servers. While the bulk of the power dissipated is dynamic switching power, leakage power is also beginning to be a concern. Chipmakers expect that in future chip generations, leakage's proportion of total chip power will increase significantly.This paper examines methods for reducing leakage power within the cache memories of the CPU. Because caches comprise much of a CPU chip's area and transistor counts, they are reasonable targets for attacking leakage. We discuss policies and implementations for reducing cache leakage by invalidating and “turning off” cache lines when they hold data not likely to be reused. In particular, our approach is targeted at the generational nature of cache line usage. That is, cache lines typically have a flurry of frequent use when first brought into the cache, and then have a period of “dead time” before they are evicted. By devising effective, low-power ways of deducing dead time, our results show that in many cases we can reduce LI cache leakage energy by 4x in SPEC2000 applications without impacting performance. Because our decay-based techniques have notions of competitive on-line algorithms at their roots, their energy usage can be theoretically bounded at within a factor of two of the optimal oracle-based policy. We also examine adaptive decay-based policies that make energy-minimizing policy choices on a per-application basis by choosing appropriate decay intervals individually for each cache line. Our proposed adaptive policies effectively reduce LI cache leakage energy by 5x for the SPEC2000 with only negligible degradations in performance.