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ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
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ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
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ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Computer architecture: a quantitative approach
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IEEE Micro
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Proceedings of the conference on Design, automation and test in Europe - Volume 1
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ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
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Leakage power will exceed dynamic power in microprocessor as feature size shrinks, especially for on-chip caches. Besides developing low leakage process and circuit, how to control the leakage power in architectural level is worth to be studied. In this paper, a PDSR (Periodically Drowsy Speculatively Recover) algorithm and its extended version with adaptivity are proposed to optimize instruction cache leakage power dissipation. SPEC CPU2000 simulation results show that, with negligible performance loss, PDSR can aggressively decrease leakage power dissipation of instruction cache. Compared with other existing methods, PDSR and adaptive PDSR achieve more satisfying and more robust energy efficiency.