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ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
A static power model for architects
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
A low-leakage dynamic multi-ported register file in 0.13mm CMOS
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Dynamic fine-grain leakage reduction using leakage-biased bitlines
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Tradeoffs in power-efficient issue queue design
Proceedings of the 2002 international symposium on Low power electronics and design
Adaptive Mode Control: A Static-Power-Efficient Cache Design
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
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Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
The Alpha 21264 Microprocessor Architecture
ICCD '98 Proceedings of the International Conference on Computer Design
Applying Decay Strategies to Branch Predictors for Leakage Energy Savings
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Static Energy Reduction Techniques for Microprocessor Caches
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Temperature-aware microarchitecture: Modeling and implementation
ACM Transactions on Architecture and Code Optimization (TACO)
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ACM Transactions on Architecture and Code Optimization (TACO)
Profile-based adaptation for cache decay
ACM Transactions on Architecture and Code Optimization (TACO)
Exploiting temporal locality in drowsy cache policies
Proceedings of the 2nd conference on Computing frontiers
A simple mechanism to adapt leakage-control policies to temperature
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Exploring the limits of leakage power reduction in caches
ACM Transactions on Architecture and Code Optimization (TACO)
Optimizing the Thermal Behavior of Subarrayed Data Caches
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Microarchitecture-level leakage reduction with data retention
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors
Proceedings of the 4th international conference on Computing frontiers
Impact of process variations on multicore performance symmetry
Proceedings of the conference on Design, automation and test in Europe
Throughput of multi-core processors under thermal constraints
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Cache leakage control mechanism for hard real-time systems
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Performance optimal processor throttling under thermal constraints
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Reducing leakage in power-saving capable caches for embedded systems by using a filter cache
MEDEA '07 Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture
On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance
IEEE Transactions on Computers
Leakage energy reduction in cache memory by data compression
ACM SIGARCH Computer Architecture News - Special issue: ALPS '07---advanced low power systems
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Microprocessors & Microsystems
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Transactions on High-Performance Embedded Architectures and Compilers II
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ACM SIGARCH Computer Architecture News
Applying decay to reduce dynamic power in set-associative caches
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
Cryptographic side-channels from low-power cache memory
Cryptography and Coding'07 Proceedings of the 11th IMA international conference on Cryptography and coding
Leakage-efficient design of value predictors through state and non-state preserving techniques
The Journal of Supercomputing
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ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
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ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
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Proceedings of the sixth ACM conference on Security and privacy in wireless and mobile networks
A survey on cache tuning from a power/energy perspective
ACM Computing Surveys (CSUR)
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This paper compares the effectiveness of state-preserving and non-state-preserving techniques for leakage control in caches by comparing drowsy cache and gated-Vss for data caches using 70nm technology parameters. To perform the comparison, we introduce "HotLeakage", a new architectural model for subthreshold and gate leakage that explicitly models the effects of temperature, voltage, and parameter variations, and has the ability to recalculate leakage currents dynamically as temperature and voltage change at runtime due to operating conditions, DVS techniques, etc.By comparing drowsy-cache and gated-Vss at different L2 latencies and different gate oxide thickness values, we are able to identify a range of operating parameters at which gated-Vss is more energy efficient than drowsy-cache, even though gated-Vss does not preserve data in cache lines that have been deactivated. We are also able to show potential further benefits of gated-Vss if an effective dynamic adaptation technique can be found. These results debunk a fairly widespread beliefthat state-preserving techniques are inherently superior to non-state-preserving techniques.