Comparative evaluation of latency reducing and tolerating techniques
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Cache design trade-offs for power and performance optimization: a case study
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Run-time adaptive cache hierarchy management via reference analysis
Proceedings of the 24th annual international symposium on Computer architecture
Prefetching Using Markov Predictors
IEEE Transactions on Computers - Special issue on cache memory and related problems
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
ACM Computing Surveys (CSUR)
Dead-block prediction & dead-block correlating prefetchers
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Reducing set-associative cache energy via way-prediction and selective direct-mapping
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Integrating loop and data transformations for global optimization
Journal of Parallel and Distributed Computing
Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
Leakage Energy Management in Cache Hierarchies
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
Synthesis of customized loop caches for core-based embedded systems
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Energy-Efficiency of VLSI Caches: A Comparative Study
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Guided region prefetching: a cooperative hardware/software approach
Proceedings of the 30th annual international symposium on Computer architecture
Adaptive mode control: A static-power-efficient cache design
ACM Transactions on Embedded Computing Systems (TECS)
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Low-leakage asymmetric-cell SRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
State-Preserving vs. Non-State-Preserving Leakage Control in Caches
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Prefetch injection based on hardware monitoring and object metadata
Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation
Single-vDD and single-vT super-drowsy techniques for low-leakage high-performance instruction caches
Proceedings of the 2004 international symposium on Low power electronics and design
Profile-based adaptation for cache decay
ACM Transactions on Architecture and Code Optimization (TACO)
Exploring the limits of leakage power reduction in caches
ACM Transactions on Architecture and Code Optimization (TACO)
Prefetching-aware cache line turnoff for saving leakage energy
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
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While numerous prior studies focused on performance and energy optimizations for caches, their interactions have received much less attention. This is unfortunate since in general the performance oriented techniques influence energy behavior of the cache, and the energy oriented techniques usually increase program execution cycles. The overall energy and performance behavior of caches in embedded systems when multiple techniques co-exist remains an open research problem. This paper first studies this interaction and demonstrates how performance and energy optimizations can affect each other. We then propose three optimization schemes that turn-off cache lines in a prefetching-sensitive manner. Specifically, these schemes treat prefetched cache lines differently from the lines brought to the cache in a normal way (i.e., through a load operation) in turning off the cache lines. Our experiments with five randomly selected codes from the SPEC2000 suite indicate that the proposed approaches save significant leakage energy. Our results also show that the performance degradations incurred by the proposed approaches are very small.