Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Design Challenges of Technology Scaling
IEEE Micro
Adaptive Mode Control: A Static-Power-Efficient Cache Design
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
EDA challenges facing future microprocessor design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Integer linear programming based energy optimization for banked DRAMs
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Exploring the limits of leakage power reduction in caches
ACM Transactions on Architecture and Code Optimization (TACO)
Low-leakage robust SRAM cell design for sub-100nm technologies
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Low-leakage SRAM Design with Dual V_t Transistors
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A case for asymmetric-cell cache memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA
Proceedings of the conference on Design, automation and test in Europe
Design and analysis of hybrid NEMS-CMOS circuits for ultra low-power applications
Proceedings of the 44th annual Design Automation Conference
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells
Proceedings of the 18th ACM Great Lakes symposium on VLSI
ILP-Based energy minimization techniques for banked memories
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Capturing and optimizing the interactions between prefetching and cache line turnoff
Microprocessors & Microsystems
Leakage minimization of SRAM cells in a dual-V t and Dual-T ox technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Case study of reliability-aware and low-power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Stacking SRAM banks for ultra low power standby mode operation
Proceedings of the 47th Design Automation Conference
Investigating the impact of NBTI on different power saving cache strategies
Proceedings of the Conference on Design, Automation and Test in Europe
Transactions on high-performance embedded architectures and compilers III
New configuration memory cells for FPGA in nano-scaled CMOS technology
Microelectronics Journal
Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM
Integration, the VLSI Journal
Proceedings of the 49th Annual Design Automation Conference
Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications
Microelectronics Journal
Fine-grain voltage tuned cache architecture for yield management under process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-leakage soft error tolerant port-less configuration memory cells for FPGAs
Integration, the VLSI Journal
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We introduce a novel family of asymmetric dual-Vt static random access memory cell designs that reduce leakage power in caches while maintaining low access latency. Our designs exploit the strong bias toward zero at the bit level exhibited by the memory value stream of ordinary programs. Compared to conventional symmetric high-performance cells, our cells offer significant leakage reduction in the zero state and, in some cases, also in the one state, albeit to a lesser extent. A novel sense amplifier, in combination with dummy bitlines, allows for read times to be on par with conventional symmetric cells. With one Cell design, leakage is reduced by 7 × (in the zero state) with no performance degradation, but with a stability degradation of 6%. Another cell design reduces leakage by 2 × (in the zero state) with no performance or stability loss. An alternative cell design reduces leakage by 58 × (in the zero state) with a performance degradation of 1% and an area increase of 2.4% and no stability degradation.