Low-leakage asymmetric-cell SRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A case for asymmetric-cell cache memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical analysis of SRAM cell stability
Proceedings of the 43rd annual Design Automation Conference
A low leakage 9t sram cell for ultra-low power operation
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Process variation tolerant SRAM array for ultra low voltage applications
Proceedings of the 45th annual Design Automation Conference
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test
Low power and high performance sram design using bank-based selective forward body bias
Proceedings of the 19th ACM Great Lakes symposium on VLSI
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
The impact of BEOL lithography effects on the SRAM cell performance and yield
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Characterization of a novel nine-transistor SRAM cell
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM
VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Single ended 6T SRAM with isolated read-port for low-power embedded systems
Proceedings of the Conference on Design, Automation and Test in Europe
Leakage Current Reduction Techniques for 7T SRAM Cell in 45 nm Technology
Wireless Personal Communications: An International Journal
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As technology continues to scale, maintaining important figures of merit of Static Random Access Memories (SRAMs), such as power dissipation and an acceptable Static Noise Margin (SNM), becomes increasingly challenging. In this paper, we address SRAM instability and power (leakage) dissipation in scaled-down technologies by presenting a novel design flow for simultaneous power minimization, performance maximization and process variation tolerance (P3) optimization of nano-CMOS circuits. The 45 and 32nm technology node standard 6-Transistor (6T) and 8T SRAM cells are used as example circuits for demonstration of the effectiveness of the flow. Thereafter, the SRAM cell is subjected to a dual threshold voltage (dual-V"T"h) assignment based on a novel statistical Design of Experiments-Integer Linear Programming (DOE-ILP) approach. Experimental results show 61% leakage power reduction and 13% increase in the read SNM. In addition, process variation analysis of the optimized cell is conducted considering the variability effect in twelve device parameters. To the best of the authors' knowledge, this is the first study which makes use of statistical DOE-ILP for optimization of conflicting targets of stability and power in the presence of process variations in SRAMs.