Intrinsic MOSFET parameter fluctuations due to random dopant placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Variability in sub-100nm SRAM designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The impact of random device variation on SRAM cell stability in sub-90-nm CMOS technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A methodology for statistical estimation of read access yield in SRAMs
Proceedings of the 45th annual Design Automation Conference
Analyzing static and dynamic write margin for nanometer SRAMs
Proceedings of the 13th international symposium on Low power electronics and design
Breaking the simulation barrier: SRAM evaluation through norm minimization
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
SRAM dynamic stability: theory, variability and analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Accuracy-aware SRAM: a reconfigurable low power SRAM architecture for mobile multimedia applications
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Analog Integrated Circuits and Signal Processing
SRAM parametric failure analysis
Proceedings of the 46th Annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Adaptive sampling for efficient failure probability analysis of SRAM cells
Proceedings of the 2009 International Conference on Computer-Aided Design
Proceedings of the 20th symposium on Great lakes symposium on VLSI
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
Reducing SRAM power using fine-grained wordline pulsewidth control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 47th Design Automation Conference
In-situ characterization and extraction of SRAM variability
Proceedings of the 47th Design Automation Conference
A holistic approach for statistical SRAM analysis
Proceedings of the 47th Design Automation Conference
A statistical simulation method for reliability analysis of SRAM core-cells
Proceedings of the 47th Design Automation Conference
A black box method for stability analysis of arbitrary SRAM cell structures
Proceedings of the Conference on Design, Automation and Test in Europe
Impact of RDF and RTS on the performance of SRAM cells
Journal of Computational Electronics
A scalable circuit-architecture co-design to improve memory yield for high-performance processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Transactions on high-performance embedded architectures and compilers III
Efficient SRAM failure rate prediction via Gibbs sampling
Proceedings of the 48th Design Automation Conference
Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM
Integration, the VLSI Journal
Unequal-error-protection codes in SRAMs for mobile multimedia applications
Proceedings of the International Conference on Computer-Aided Design
A fast estimation of SRAM failure rate using probability collectives
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Exploiting narrow-width values for process variation-tolerant 3-D microprocessors
Proceedings of the 49th Annual Design Automation Conference
Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes
Journal of Electronic Testing: Theory and Applications
Proceedings of the 2013 ACM international symposium on International symposium on physical design
A low power 6t-SRAM using negative bit-line for variability tolerance beyond 22nm node
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Statistical SRAM read access yield improvement using negative capacitance circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Techniques for compensating memory errors in JPEG2000
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cross entropy minimization for efficient estimation of SRAM failure rate
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Modeling the impact of permanent faults in caches
ACM Transactions on Architecture and Code Optimization (TACO)
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The impact of process variation on SRAM yield has become a serious concern in scaled technologies. In this paper, we propose a methodology to analyze the stability of an SRAM cell in the presence of random fluctuations in the device parameters. We provide a theoretical framework for characterizing the DC noise margin of a memory cell and develop models for estimating the cell failure probabilities during read and write operations. The proposed models are verified against extensive Monte-Carlo simulations and are shown to match well over the entire range of the distributions well beyond the 3-sigma extreme.