Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Measurement and Characterization of 6T SRAM Cell Current
MTDT '05 Proceedings of the 2005 IEEE International Workshop on Memory Technology, Design, and Testing
A Design for Test Technique for Parametric Analysis of SRAM: On-Die Low Yield Analysis
ITC '04 Proceedings of the International Test Conference on International Test Conference
Statistical analysis of SRAM cell stability
Proceedings of the 43rd annual Design Automation Conference
High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
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Measurement and extraction of as fabricated SRAM cell variability is essential to process improvement and robust design. This is challenging in practice, due to the complexity in the test procedure and requisite numerical analysis. This work proposes a new singleended test procedure for SRAM cell write margin measurement. Moreover, an efficient decomposition method is developed to extract transistor threshold voltage (VTH) variations from the measurements, allowing accurate determination of SRAM cell stability. The entire approach is demonstrated in a 90nm test chip with 32K cells. The advantages of the proposed method include: (1) a single-ended SRAM test structure with no disturbance to SRAM operations; (2) a convenient test procedure that only requires quasistatic control of external voltages; and (3) a non-iterative method that extracts the VTH variation of each transistor from eight measurements. The new procedure enables accurate predictions of SRAM performance variability. As validated with 90nm data of write margin and data retention voltage, the prediction error from extracted VTH variations is