Impact of Interconnect Process Variations on Memory Performance and Design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Breaking the simulation barrier: SRAM evaluation through norm minimization
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
In-situ characterization and extraction of SRAM variability
Proceedings of the 47th Design Automation Conference
Error-Aware Algorithm/Architecture Coexploration for Video Over Wireless Applications
ACM Transactions on Embedded Computing Systems (TECS)
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High-density and high-performance single-port anddual-port SRAM increasingly occupy a majority of thechip area in System-on-Chip product designs. Therefore,good yieldability and manufacturability of theSRAM are essential. At the same time there is tremendouscompetitive pressure to get the best SRAM densityand performance. We have previously published andpresented the industry's smallest and fastest embedded6T SRAM bitcells in 0.18um and 130nm generationstandard CMOS process [1]. We have described howthese SRAM bitcells are robust by design even whileaggressively driving density and performance. In thispaper we discuss the design and use of SRAM-specifictest structures that have enabled us to quickly evaluateprocess-design interactions [2] and to fine-tune processand/or design for improving yields and manufacturability.We have designed test structures using our aggressiveproduction bitcell as basis to probe for any possibleweaknesses of the process or design in SRAM. Resultsfrom these SRAM-specific test structures show goodcorrelation to yield results and in-line SEM observations,and enable us to improve SRAM yields quickly.We have also designed SRAM-transistor test structuresto characterize the SRAM cell devices in their realworking environment. Results help to evaluate the circuitperformance and provide us with guidelines forfurther design improvements. These data when used inthe early stage of the development cycle are also usefulfor model validation.