Statistical Modeling for Circuit Simulation
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Impact of Interconnect Process Variations on Memory Performance and Design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Variation tolerant 9T SRAM cell design
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Reducing SRAM power using fine-grained wordline pulsewidth control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 48th Design Automation Conference
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It has been recognized that as CMOS technology scales, the accompanied scaling of the conventional 6T-SRAM bitcell will require careful assessment of the role of device variations on its stability, electrical performance and leakage. As part of our SRAM design methodology, we have studied the statistics of local and across-wafer variations in bitcell-related parameters by using a series of specialized electrical test structures. The resulting quantification of the device variations are useful towards developing accurate mismatch models that can in turn be used to design not only robust SRAM bitcells but also functionally robust memory arrays wherein the role of bitline leakage and the statistics of 'tail-bits' are