Variation tolerant 9T SRAM cell design

Authors:
Sreeharsha Tavva;Dhireesha Kudithipudi
Affiliations:
Rochester Institute of Technology, Rochester, NY, USA;Rochester Institute of Technology, Rochester, NY, USA
Venue:
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Year:
2010

Citing 7
Cited 0

Variability in sub-100nm SRAM designs

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
The impact of random device variation on SRAM cell stability in sub-90-nm CMOS technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Highly-Stable Nanometer Memory for Low-Power Design

NDCS '08 Proceedings of the 2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test
Embedded Memories for Nano-Scale VLSIs

Embedded Memories for Nano-Scale VLSIs
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Nanoscale SRAM memory design has become increasingly challenging due to the reducing noise margins and increased sensitivity to threshold voltage variations. These issues oppose our ability to achieve stable bitcells and acceptable performance while maintaining density using the standard six-transistor(6T) circuit. To overcome these challenges, researchers have proposed different topologies for SRAMs with single-ended 8T, 9T, 10T bitcell designs. These designs improve the cell stability in the subthreshold regime but suffer from bit-line leakage noise, placing constraints on the number of cells shared by each bitline. In this paper, we propose a novel 9T SRAM cell topology which achieves both cell stability as well as prevents bit-line leakage. With the proposed 9T SRAM circuit, the read static noise margin is nearly twice that of conventional 6T SRAM circuit. Furthermore, the bitline leakage power consumption of the proposed 9T SRAM cell is reduced by up to 79\%, 76\% and 39\% when compared to the previously published 8T, 10T and 9T SRAM cells, respectively.