Intrinsic MOSFET parameter fluctuations due to random dopant placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Review and future prospects of low-voltage RAM circuits
IBM Journal of Research and Development
Statistically Aware SRAM Memory Array Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Analysis of Process Variation's Effect on SRAM's Read Stability
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical analysis of SRAM cell stability
Proceedings of the 43rd annual Design Automation Conference
Analytical modeling of SRAM dynamic stability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Compiler-Directed Variable Latency Aware SPM Management to CopeWith Timing Problems
Proceedings of the International Symposium on Code Generation and Optimization
Proceedings of the conference on Design, automation and test in Europe
Block remap with turnoff: a variation-tolerant cache design technique
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Invited paper: Variability in nanometer CMOS: Impact, analysis, and minimization
Integration, the VLSI Journal
The impact of random device variation on SRAM cell stability in sub-90-nm CMOS technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A methodology for statistical estimation of read access yield in SRAMs
Proceedings of the 45th annual Design Automation Conference
Leakage minimization of SRAM cells in a dual-V t and Dual-T ox technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Breaking the simulation barrier: SRAM evaluation through norm minimization
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
SRAM parametric failure analysis
Proceedings of the 46th Annual Design Automation Conference
Adaptive sampling for efficient failure probability analysis of SRAM cells
Proceedings of the 2009 International Conference on Computer-Aided Design
DRAM-based FPGA enabled by three-dimensional (3d) memory stacking (abstract only)
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Variation tolerant 9T SRAM cell design
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Statistical design of the 6T SRAM bit cell
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Reducing SRAM power using fine-grained wordline pulsewidth control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Emerging sensing techniques for emerging memories
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Leakage-aware redundancy for reliable sub-threshold memories
Proceedings of the 48th Design Automation Conference
Universal statistical cure for predicting memory loss
Proceedings of the International Conference on Computer-Aided Design
Variation tolerant sensing scheme of spin-transfer torque memory for yield improvement
Proceedings of the International Conference on Computer-Aided Design
A fast estimation of SRAM failure rate using probability collectives
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Process variation aware data management for STT-RAM cache design
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Effects of process variation on the access time in SRAM cells
Euro-Par'12 Proceedings of the 18th international conference on Parallel processing workshops
Voltage driven nondestructive self-reference sensing scheme of spin-transfer torque memory
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical SRAM read access yield improvement using negative capacitance circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cross entropy minimization for efficient estimation of SRAM failure rate
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the International Conference on Computer-Aided Design
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Many components of variability become larger percentage design factors with decreasing feature size. Hence, the small transistors in SRAM cells are particularly sensitive to these variations. The SRAM cell transistors in sub-100-nm designs may contain fewer than 100 channel dopant atoms. To achieve a robust design with such variability, one must enhance the normal static-noise-margin and write-trip-point analysis, often with Monte Carlo simulations using statistical transistor models including the process and mismatch fluctuations. Similar challenges exist for the sense amplifiers normally used with SRAM arrays. Except with very low speed designs, yield to speed can be substantially reduced by variations between nominally matched sense amplifier transistors as well as by the variability resulting in a very worst memory cell low read current. This also increases the hazards of delay timing with dummy paths and dummy cells and increases the need for at-speed testing prior to repair.