Universal switch blocks for three-dimensional FPGA design
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Rothko: A Three-Dimensional FPGA
IEEE Design & Test
Wiring requirement and three-dimensional integration technology for field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Review and future prospects of low-voltage RAM circuits
IBM Journal of Research and Development
Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Logic-based eDRAM: origins and rationale for use
IBM Journal of Research and Development - Electrochemical technology in microelectronics
Variability in sub-100nm SRAM designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Three-dimensional place and route for FPGAs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Designing a 3-D FPGA: switch box architecture and thermal issues
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
3D configuration caching for 2D FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
High-performance, cost-effective heterogeneous 3D FPGA architectures
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Performance Benefits of Monolithically Stacked 3-D FPGA
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Motivated by the emerging three-dimensional (3D integration technologies, this paper studies the potential of applying 3D memory stacking to enable FPGA devices use on-chip DRAM cells to store configuration data. In current design practice, FPGAs do not use on-chip DRAM cells for configuration data storage mainly because on-chip DRAM self-refreshing involves destructive DRAM read operations. This problem can be solved if we use a 3D stacked memory as primary FPGA configuration data storage and externally refresh on-chip DRAM cells. Since the 3D stacked memory can easily store multiple sets of configuration data, it can meanwhile enable high-speed FPGA dynamic reconfiguration. In this paper, we study such DRAM-based FPGA design enabled by 3D memory stacking and investigate potential design issues, and employ the VPR tool set to demonstrate that DRAM-based FPGAs can noticeably reduce FPGA die area and hence improve speed and energy consumption performance, compared their SRAM-based counterparts.