TORCH: a design tool for routing channel segmentation in FPGAs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
The amorphous FPGA architecture
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
IEEE Transactions on Circuits and Systems Part I: Regular Papers
DRAM-based FPGA enabled by three-dimensional (3d) memory stacking (abstract only)
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memory
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
FPGA architecture optimisation using geometric programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Monolithically stackable hybrid FPGA
Proceedings of the Conference on Design, Automation and Test in Europe
Exploring FPGA routing architecture stochastically
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Can we go towards true 3-D architectures?
Proceedings of the 48th Design Automation Conference
A framework for architecture-level exploration of 3-D FPGA platforms
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
mrFPGA: A novel FPGA architecture with memristor-based reconfiguration
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Ultra-fine grain FPGAs: A granularity study
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Three-dimensional Integrated Circuits: Design, EDA, and Architecture
Foundations and Trends in Electronic Design Automation
Proceedings of the great lakes symposium on VLSI
Interlaced switch boxes placement for three-dimensional FPGA architecture design
International Journal of Circuit Theory and Applications
Defect tolerance in nanodevice-based programmable interconnects: utilization beyond avoidance
Proceedings of the 50th Annual Design Automation Conference
Cell transformations and physical design techniques for 3D monolithic integrated circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Cad and routing architecture for interposer-based multi-FPGA systems
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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The performance benefits of a monolithically stacked three-dimensional (3-D) field-programmable gate array (FPGA), whereby the programming overhead of an FPGA is stacked on top of a standard CMOS layer containing logic blocks (LBs) and interconnects, are investigated. A Virtex-II-style two-dimensional (2-D) FPGA fabric is used as a baseline architecture to quantify the relative improvements in logic density, delay, and power consumption achieved by such a 3-D FPGA. It is assumed that only the switch transistor and configuration memory cells can be moved to the top layers and that the 3-D FPGA employs the same LB and programmable interconnect architecture as the baseline 2-D FPGA. Assuming they are les 0.7, the area of a static random-access memory cell and switch transistors having the same characteristics as n-channel metal-oxide-semiconductor devices in the CMOS layer are used. It is shown that a monolithically stacked 3-D FPGA can achieve 3.2 times higher logic density, 1.7 times lower critical path delay, and 1.7 times lower total dynamic power consumption than the baseline 2-D FPGA fabricated in the same 65-nm technology node