Segmented channel routing in nearly as efficient as channel routing (and just as hard)
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
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ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Directional bias and non-uniformity in FPGA global routing architectures
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
FPGA routing architecture: segmentation and buffering to optimize speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
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FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Customized regular channel design in FPGAs
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General Models and a Reduction Design Technique for FPGA Switch Box Designs
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VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
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ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Design of Interconnection Networks for Programmable Logic
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Totem: Custom Reconfigurable Array Generation
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
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WISICT '05 Proceedings of the 4th international symposium on Information and communication technologies
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ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
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ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
TORCH: a design tool for routing channel segmentation in FPGAs
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Effect of the prefabricated routing track distribution on FPGA area-efficiency
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Crosspoint complexity of sparse crossbar concentrators
IEEE Transactions on Information Theory
Matching-based algorithm for FPGA channel segmentation design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power modeling and characteristics of field programmable gate arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance Benefits of Monolithically Stacked 3-D FPGA
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper proposes a systematic strategy to efficiently explore the design space of field-programmable gate array (FPGA) routing architectures. The key idea is to use stochastic methods to quickly locate near-optimal solutions in designing FPGA routing architectures without exhaustively enumerating all design points. The main objective of this paper is not as much about the specific numerical results obtained, as it is to show the applicability and effectiveness of the proposed optimization approach. To demonstrate the utility of the proposed stochastic approach, we developed the tool for optimizing routing architecture (TORCH) software based on the versatile place and route tool [1]. Given FPGA architecture parameters and a set of benchmark designs, TORCH simultaneously optimizes the routing channel segmentation and switch box patterns using the performance metric of average interconnect power-delay product estimated from placed and routed benchmark designs. Special techniques--such as incremental routing, infrequent placement, multi-modal move selection, and parallelized metric evaluation-- are developed to reduce the overall run time and improve the quality of results. Our experimental results have shown that the stochastic design strategy is quite effective in co-optimizing both routing channel segmentation and switch patterns. With the optimized routing architecture, relative to the performance of our chosen architecture baseline, TORCH can achieve average improvements of 24% and 15% in delay and power consumption for the 20 largest Microelectronics Center of North Carolina benchmark designs, and 27% and 21% for the eight benchmark designs synthesized with the Altera Quartus II University Interface Program tool. Additionally, we found that the average segment length in an FPGA routing channel should decrease with technology scaling. Finally, we demonstrate the versatility of TORCH by illustrating how TORCH can be used to optimize other aspects of the routing architecture in an FPGA.