TORCH: a design tool for routing channel segmentation in FPGAs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Exploring FPGA routing architecture stochastically
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
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In this paper, we study the problem of customized regular segmentation design in FPGA routing channels. We propose a deterministic algorithm for segmentation design problem in which each interval is assigned to only one segment (1-Segmentation). We solve the problem of maximum number of incremental track assignment of intervals by mincost network flow technique for 1-Segmentation design. The general K-Segmentation design problem can also be solved by some modifications in our algorithm. We have experimented our algorithm on a set of MCNC benchmarks and compared the routability of the segmented channels with the routability of different segmentations in FPGA routing architectures, one used by industrial Xilinx TM 4000 FPGA series. The experimental results show that the routability of the segmentation in general-purpose architecture can be as low as 18.4% while the routability of our proposed customized segmentation can be as high as 91%. This result shows the gap between the general FPGA routing architecture and customized architecture for a given application can be very significant and our method is capable of generating such optimized segmentation with high routability for a given application.