On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A performance and routablity driven router for FPGAs considering path delays
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
New performance-driven FPGA routing algorithms
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Universal switch modules for FPGA design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the optimal four-way switch box routing structures of FPGA greedy routing architectures
Integration, the VLSI Journal
Generic Universal Switch Blocks
IEEE Transactions on Computers
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Graph Theory With Applications
Graph Theory With Applications
Graph based analysis of 2-D FPGA routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Augmented disjoint switch boxes for FPGAs
WISICT '05 Proceedings of the 4th international symposium on Information and communication technologies
Crossbar based design schemes for switch boxes and programmable interconnection networks
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes
IEEE Transactions on Computers
A New Approach for Rearrangeable Multicast Switching Networks
COCOA '09 Proceedings of the 3rd International Conference on Combinatorial Optimization and Applications
Exploring FPGA routing architecture stochastically
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
An edge ordering problem of regular hypergraphs
COCOON'06 Proceedings of the 12th annual international conference on Computing and Combinatorics
Interlaced switch boxes placement for three-dimensional FPGA architecture design
International Journal of Circuit Theory and Applications
| Hi-index | 14.98 |
An FPGA switch box is said to be hyper-universal if it is detailed-routable for any set of multipin nets specifying a routing requirement over the switch box. Comparing with the known 驴universal switch modules,驴 where only 2-pin nets are considered, the hyper-universal switch box model is more general and powerful. This paper studies the generic problem and proposes a systematic designing methodology for hyper-universal (k, W){\hbox{-}}{\rm switch} boxes, where k is the number of sides and W is the number of terminals on each side. We formulate this hyper-universal (k, W){\hbox{-}}{\rm switch} box design problem as a k{\hbox{-}}{\rm partite} graph design problem and propose an efficient reduction design technique. Applying this technique, we can design hyper-universal (k, W){\hbox{-}}{\rm switch} boxes with low O(W) switches for any fixed k. For illustration, we provide optimum hyper-universal (2, W) and (3, W){\hbox{-}}{\rm switch} boxes and a hyper-universal (4, W){\hbox{-}}{\rm switch} box with switch number quite close to the lower bound 6W, which is used in a well-known commercial design without hyper-universal routability. We also conclude that the proposed reduction method can yield an efficient detailed routing algorithm for any given routing requirement as well.