New performance-driven FPGA routing algorithms
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Orthogonal greedy coupling: a new optimization approach to 2-D FPGA routing
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Universal switch modules for FPGA design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Universal switch-module design for symmetric-array-based FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
FPGA routing and routability estimation via Boolean satisfiability
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Interconnect complexity-aware FPGA placement using Rent's rule
Proceedings of the 2001 international workshop on System-level interconnect prediction
On optimum switch box designs for 2-D FPGAs
Proceedings of the 38th annual Design Automation Conference
The management of applications for reconfigurable computing using an operating system
CRPIT '02 Proceedings of the seventh Asia-Pacific conference on Computer systems architecture
General models for optimum arbitrary-dimension FPGA switch box designs
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
General Models and a Reduction Design Technique for FPGA Switch Box Designs
IEEE Transactions on Computers
On improving FPGA routability applying multi-level switch boxes
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
FPGA vs. multi-core CPUs vs. GPUs: hands-on experience with a sorting application
Facing the multicore-challenge
FPGA vs. multi-core CPUs vs. GPUs: hands-on experience with a sorting application
Facing the multicore-challenge
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Several industrial FPGA routing architectures have been shown to have no efficient routing algorithms (unless P=NP). Here, we further investigate if the intractability of the routing problem on a regular 2-D FPGA routing architecture can be alleviated by adding routing switches. We show that on this routing architecture, even with a substantial increase in switching flexibility, a polynomial time, predictable routing algorithm is still not likely to exist, and there is no constant ratio bound of the detailed over global routing channel densities. We also show that a perfect routing is unachievable on this architecture even with near complete (maximum) switching flexibility.We also discuss a new, greedy routing architecture, that possesses predictable and other desired routing properties, yet requires fewer routing resources than regular architectures. This theoretical result may suggest an alternative approach in routing architecture designs.