Interconnect complexity-aware FPGA placement using Rent's rule

Authors:
G. Parthasarathy;M. Marek-Sadowska;Arindam Mukherjee;Amit Singh
Affiliations:
Univ. of California, Santa Barbara;Univ. of California, Santa Barbara;Univ. of California, Santa Barbara;Univ. of California, Santa Barbara
Venue:
Proceedings of the 2001 international workshop on System-level interconnect prediction
Year:
2001

Citing 9
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On the intrinsic rent parameter and spectra-based partitioning methodologies

EURO-DAC '92 Proceedings of the conference on European design automation
On routability prediction for field-programmable gate arrays

DAC '93 Proceedings of the 30th international Design Automation Conference
On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
An architecture-independent approach to FPGA routing based on multi-weighted graphs

EURO-DAC '94 Proceedings of the conference on European design automation
FPGA routing and routability estimation via Boolean satisfiability

FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100% LUT utilization)

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
VPR: A new packing, placement and routing tool for FPGA research

FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Graph based analysis of 2-D FPGA routing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Generating synthetic benchmark circuits for evaluating CAD tools

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Efficient circuit clustering for area and power reduction in FPGAs

FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
On metrics for comparing routability estimation methods for FPGAs

Proceedings of the 39th annual Design Automation Conference
Efficient circuit clustering for area and power reduction in FPGAs

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Rapid and Reliable Routability Estimation for FPGAs

FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits

FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Congestion minimization during placement without estimation

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
On Routing Demand and Congestion Estimation for FPGAs

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Defect tolerance for nanocomputer architecture

Proceedings of the 2004 international workshop on System level interconnect prediction
On metrics for comparing interconnect estimation methods for FPGAs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimality and scalability study of existing placement algorithms

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Architecture-aware FPGA placement using metric embedding

Proceedings of the 43rd annual Design Automation Conference
Microminiature packaging and integrated circuitry: the work of E. F. Rent, with an application to on-chip interconnection requirements

IBM Journal of Research and Development - POWER5 and packaging
Congestion estimation and localization in fpgas:: a visual tool for interconnect prediction

Proceedings of the 2007 international workshop on System level interconnect prediction
Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

Field Programmable Gate Arrays (FPGAs) have gained in commercial acceptance because they offer instant manufacturing turnaround and low costs. However, FPGAs are constantly hard pressed to keep up with the requirements of the more complex and larger scale circuits which are being targeted for them. Routability of a circuit depends on the FPGA architecture, the placement, and the interconnection complexity of the circuit to be placed and routed. This paper explores the use of Rent's rule as a complexity metric for improving the placement of circuits on a target FPGA architecture, such that routing resource utilization is improved. A new simulated annealing based placement algorithm is presented and experimental results are presented to illustrate the validity of the approach for certain example circuits and the ISCAS benchmarks.