Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
Hierarchical interconnection structures for field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interconnect complexity-aware FPGA placement using Rent's rule
Proceedings of the 2001 international workshop on System-level interconnect prediction
Estimating routing congestion using probabilistic analysis
Proceedings of the 2001 international symposium on Physical design
Low Power Digital CMOS Design
Teramac-configurable custom computing
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Congestion estimation during top-down placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Defect tolerant architectures will be mandatory for building economical and cheap computing systems with billions of devices of nanometer dimension because it will contain significant number of defects due to statistical variations. The basic idea behind a defect tolerant custom configurable system is to build the system out of partially perfect components, detect the defects and configure the available good resources using software. In this paper we discuss implications of defect tolerance on power, area, delay and other relevant parameters for computing architectures. The additional requirement of a scalable configuration mechanism, redundant components and detection scheme necessitates extra burden on the interconnect to sustain it. Through back-of-envelope calculations using a priori wire length estimation and intuitive arguments we will illustrate the hidden cost of supporting such an architecture.