Multiple-Way Network Partitioning
IEEE Transactions on Computers
Introduction to programmable active memories
Systolic array processors
A general purpose multiple way partitioning algorithm
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
An Improved Min-Cut Algonthm for Partitioning VLSI Networks
IEEE Transactions on Computers
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
Plasma: an FPGA for million gate systems
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Cube-4—a scalable architecture for real-time volume rendering
Proceedings of the 1996 symposium on Volume visualization
The Transmogrifier-2: a 1 million gate rapid prototyping system
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Fast integrated tools for circuit design with FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Active pages: a computation model for intelligent memory
Proceedings of the 25th annual international symposium on Computer architecture
Computer Vision Algorithms on Reconfigurable Logic Arrays
IEEE Transactions on Parallel and Distributed Systems
Exploiting ILP in page-based intelligent memory
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Generating highly-routable sparse crossbars for PLDs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Readings in hardware/software co-design
Reconfigurable Computing for Digital Signal Processing: A Survey
Journal of VLSI Signal Processing Systems
Designing and Debugging Custom Computing Applications
IEEE Design & Test
Memory Access Schemes for Configurable Processors
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Defect tolerance for nanocomputer architecture
Proceedings of the 2004 international workshop on System level interconnect prediction
Nanocomputing in the presence of defects and faults: a survey
Nano, quantum and molecular computing
Design, Debug, Deploy: The Creation of Configurable Computing Applications
Journal of Signal Processing Systems
The StageNet fabric for constructing resilient multicore systems
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Effect of increasing chip density on the evolution of computer architectures
IBM Journal of Research and Development
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
Cube-4 implementations on the teramac custom computing machine
EGGH'96 Proceedings of the Eleventh Eurographics conference on Graphics Hardware
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Abstract: The Teramac configurable hardware system can execute synchronous logic designs of up to one million gates at rates up to 1 megahertz. A fully configured Teramac includes half a gigabyte of RAM and hardware support for large multiported register files. The system has been built from custom FPGA's packaged in large multichip modules (MCMs). A large custom circuit (/spl sim/1,000,000 gates) may be compiled onto the hardware in approximately 2 hours, without user intervention. The system is being used to explore the potential of custom computing machinery (CCM).