SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
Programmable active memories: reconfigurable systems come of age
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Efficient Logic Emulation System
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Teramac-configurable custom computing
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
The Transmogrifier C hardware description language and compiler for FPGAs
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Hierarchical partitioning for field-programmable systems
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A hybrid complete-graph partial-crossbar routing architecture for multi-FPGA systems
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
A fast routability-driven router for FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Trading quality for compile time: ultra-fast placement for FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Multi-terminal net routing for partial crossbar-based multi-FPGA systems
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Innovative system-level design environment based on FORM for transport processing system
Proceedings of the conference on Design, automation and test in Europe
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
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FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
PuMA++: From Behavioral Specification to Multi-FPGA-Prototype
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
A New Placement Method for Direct Mapping into LUT-Based FPGAs
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Prototyping Framework for Reconfigurable Processors
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Multiterminal net routing for partial crossbar-based multi-FPGA systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper describes the Transmogrifier-2, a second generation multi-FPGA system. The largest version of the system will comprise 16 boards that each contain two Altera 10K50 FPGAs, four I-cube interconnect chips, and up to 8 Mbytes of memory. The inter-FPGA routing architecture of the TM-2 uses a novel interconnect structure, a non-uniform partial crossbar, that provides a constant delay between any two FPGAs in the system. The TM-2 architecture is modular and scalable, meaning that various sized systems can be constructed from the same board, while maintaining routability and the constant delay feature. Other features include a system-level programmable clock that allows single-cycle access to off-chip memory, and programmable clock waveforms with resolution to 10ns. The first Transmogrifier-2 boards have been manufactured and are functional. They have recently been used successfully in some simple graphics acceleration applications.