Statecharts: A visual formalism for complex systems
Science of Computer Programming
A system for compiling and debugging structured data processing controllers
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
The Transmogrifier-2: a 1 million gate rapid prototyping system
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Design and synthesis of array structured telecommunication processing applications
DAC '97 Proceedings of the 34th annual Design Automation Conference
FORM: A Frame-Oriented Representation Method for Digital Telecommunication System Design
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Reconfigurable real-time signal transport system using custom FPGAs
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Matisse: A System-on-Chip Design Methodology Emphasizing Dynamic Memory Management
Journal of VLSI Signal Processing Systems - Special issue on system level design
Transmutable Telecom System and Its Application
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Exploration and Synthesis of Dynamic Data Sets in Telecom Network Applications
Proceedings of the 12th international symposium on System synthesis
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This paper presents a system-level design environment for data transport processing systems. In this environment, designers can easily verify system behavior by formally defining data structures and their related actions, without considering detailed timing. In addition, the verified specification can be translated into synthesizable RTL descriptions by a dedicated RTL generator. Thus, using lower-level EDA tools, actual hardware can be obtained directly from a system-level specification.