Statecharts: A visual formalism for complex systems
Science of Computer Programming
The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
A system for compiling and debugging structured data processing controllers
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Controller optimization for protocol intensive applications
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Transmission Networking: Sonet and the Synchronous Digital Hierarchy
Transmission Networking: Sonet and the Synchronous Digital Hierarchy
Partitioning and optimizing controllers synthesized from hierarchical high-level descriptions
DAC '98 Proceedings of the 35th annual Design Automation Conference
Design of a SPDIF receiver using protocol compiler
DAC '98 Proceedings of the 35th annual Design Automation Conference
Innovative system-level design environment based on FORM for transport processing system
Proceedings of the conference on Design, automation and test in Europe
Extensible control architectures
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
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This paper describes an automated design andsynthesis methodology for telecommunications ASIC's.Array frames, an array structured visualization of theprocessing problem, are used in the specification anddebugging of the design. This allows design much closer to thespecification level. The array frame concept is integratedinto the Dali structured control logic design environment. AnSDH (Synchronous Digital Hierarchy) style exampledemon-strates the use of array frames. The array frame approachwas successfully applied in industrial applications.