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LUSTRE: a declarative language for real-time programming
POPL '87 Proceedings of the 14th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Synchronous programming with events and relations: the SIGNAL language and its semantics
Science of Computer Programming
The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
A system for compiling and debugging structured data processing controllers
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Controller optimization for protocol intensive applications
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Design and synthesis of array structured telecommunication processing applications
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multi-processor performance on the Tera MTA
SC '98 Proceedings of the 1998 ACM/IEEE conference on Supercomputing
High-Level specification and automatic generation of IP interface monitors
Proceedings of the 39th annual Design Automation Conference
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Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A case study of multi-threading in the embedded space
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
PyPBS design and methodologies
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
A case study of multi-threading in the embedded space
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
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Architectural advances of modern systems has often been at odds with control complexity, requiring significant effort in both design and verification. This is particularly true for sequential controllers, where machine complexity can quickly surpass designer ability. Traditional solutions to this problem require elaborate specifications that are difficult to maintain and extend. Further, the logic generated from these specifications bares no resemblance to the intended behavior and often fails to meet design performance constraints. In the process of designing a multi-threaded, dynamically-pipelined microcontroller, we encountered a number of common difficulties that arise from the inadequacies of traditional pipeline design methodologies. Through the use of a novel nondeterministic finite automata (NFA) specification model, we were able to implement an extensible control structure with minimal design effort. In this paper we present a viable pipeline controller specification methodology using the pyPBS language, which enables minimal effort control partitioning and compact behavioral representation. The structure of the language encourages design decisions that promote efficient modular constructions which can be easily integrated and extended. We present an overview of the our methodology including background on the pyPBS synthesis model, an architectural overview of our multi-threaded microcontroller, and implementation details for the control structure of the design including the complete control specifications. In addition, we show that the applicative nature of the pyPBS language allows for addition of a multi-cycle multiplication unit with minimal effort.