An efficient implementation of reactivity for modeling hardware in the scenic design environment
DAC '97 Proceedings of the 34th annual Design Automation Conference
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Term rewriting and all that
ECL: a specification environment for system-level design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proof, language, and interaction
The VERILOG Hardware Description Language
The VERILOG Hardware Description Language
A Model and Methodology for Hardware-Software Codesign
IEEE Design & Test
Hardware Synthesis from Term Rewriting Systems
VLSI '99 Proceedings of the IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration: Systems on a Chip
High level compilation for fine grained FPGAs
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Parallelizing Applications into Silicon
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Microprocessor Specification in Hawk
ICCL '98 Proceedings of the 1998 International Conference on Computer Languages
The Transmogrifier C hardware description language and compiler for FPGAs
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
High-level modeling and FPGA prototyping of microprocessors
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Symbolic NFA scheduling of a RISC microprocessor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modular scheduling of guarded atomic actions
Proceedings of the 41st annual Design Automation Conference
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
High-level synthesis: an essential ingredient for designing complex ASICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An algebraic theory for behavioral modeling and protocol synthesis in system design
Formal Methods in System Design
Behavioral type inference: part I - algebraic theory for bahavioral type inference
Formal methods and models for system design
Extensible control architectures
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Synthesizing synchronous elastic flow networks
Proceedings of the conference on Design, automation and test in Europe
Flexible hardware-software cooperation system with HwModule board and co-design framework by ET
ACACOS'08 Proceedings of the 7th WSEAS International Conference on Applied Computer and Applied Computational Science
Synthesis from multi-cycle atomic actions as a solution to the timing closure problem
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Correct-by-construction microarchitectural pipelining
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Bounded dataflow networks and latency-insensitive circuits
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Suitability of mCRL2 for concurrent-system design: a 2 × 2 switch case study
FMCO'09 Proceedings of the 8th international conference on Formal methods for components and objects
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Most hardware description frameworks, whether schematic or textual, use cooperating finite state machines (CFSM) as the underlying abstraction. In the CFSM framework, a designer explicitly manages the concurrency by scheduling the exact cycle-by-cycle interactions between multiple concurrent state machines. Design mistakes are common in coordinating interactions between two state machines because transitions in different state machines are not semantically coupled. It is also difficult to modify one state machine without considering its interaction with the rest of the system.This paper presents a method for hardware synthesis from an "operation centric" description, where the behavior of a system is described as a collection of "atomic" operations in the form of rules. Typically, a rule is defined by a predicate condition and an effect on the state of the system. The atomicity requirement simplifies the task of hardware description by permitting the designer to formulate each rule as if the rest of the system is static.An implementation can execute several rules concurrently in a clock cycle, provided some sequential execution of those rules can reproduce the behavior of the concurrent execution. In fact, detecting and scheduling valid concurrent execution of rules is the central issue in hardware synthesis from operation-centric descriptions. The result of this paper shows that an operation-centric framework offers significant reduction in design time, without loss in implementation quality.