Parallel program design: a foundation
Parallel program design: a foundation
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
ISDL: an instruction set description language for retargetability
DAC '97 Proceedings of the 34th annual Design Automation Conference
Specifying Concurrent Program Modules
ACM Transactions on Programming Languages and Systems (TOPLAS)
Synthesis of operation-centric hardware descriptions
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
The Murphi Verification System
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Action Systems in Pipelined Processor Design
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Architecture Implementation Using the Machine Description Language LISA
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
High-level synthesis: an essential ingredient for designing complex ASICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Tackling an abstraction gap: co-simulating SystemC DE with bluespec ESL
Proceedings of the conference on Design, automation and test in Europe
Synthesizing synchronous elastic flow networks
Proceedings of the conference on Design, automation and test in Europe
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Synthesis from multi-cycle atomic actions as a solution to the timing closure problem
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Soft connections: addressing the hardware-design modularity problem
Proceedings of the 46th Annual Design Automation Conference
Translating concurrent action oriented specifications to synchronous guarded actions
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
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A modular synthesis flow is essential for a scalable and hierarchical design methodology. This paper considers a particular modular flow where each module has interface methods and the internal behavior of the module is described in terms of a set of guarded atomic actions on the state elements of the module. A module can also read and update the state of other modules but only by invoking the interface methods of those modules. This paper extends the past work on hardware synthesis of a set of guarded atomic actions by Hoe and Arvind to modules of such actions. It presents an algorithm that, given the scheduling constraints on the interface methods of the called modules, derives the "glue logic" and the scheduling constraints for the interface methods of the calling module such that the atomicity of the guarded actions is preserved across module boundaries. Such modules provide reusable IP which facilitates "correctness by construction" design methodology. It also reduces compile-times dramatically in comparison to the compilation that flattens all the modules first.