DSP design tool requirements for embedded systems: a telecommunications industrial perspective
Journal of VLSI Signal Processing Systems - Special issue on design environments for DSP
Journal of VLSI Signal Processing Systems - Special issue on design environments for DSP
CodeSyn: a retargetable code synthesis system (abstract)
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Insulin: An Instruction Set Simulation Environment
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
The mimola design system: Tools for the design of digital processors
DAC '84 Proceedings of the 21st Design Automation Conference
Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator
DAC '98 Proceedings of the 35th annual Design Automation Conference
HDL-based modeling of embedded processor behavior for retargetable compilation
Proceedings of the 11th international symposium on System synthesis
A unified formal model of ISA and FSMD
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A methodology for accurate performance evaluation in architecture exploration
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
LISA—machine description language for cycle-accurate models of programmable DSP architectures
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Memory aware compilation through accurate timing extraction
Proceedings of the 37th Annual Design Automation Conference
Predicting performance potential of modern DSPs
Proceedings of the 37th Annual Design Automation Conference
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Retargetable compiled simulation of embedded processors using a machine description language
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Generating production quality software development tools using a machine description language
Proceedings of the conference on Design, automation and test in Europe
Retargetable estimation scheme for DSP architecture selection
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Hardware/software instruction set configurability for system-on-chip processors
Proceedings of the 38th annual Design Automation Conference
Static resource models of instruction sets
Proceedings of the 14th international symposium on Systems synthesis
Functional abstraction driven design space exploration of heterogeneous programmable architectures
Proceedings of the 14th international symposium on Systems synthesis
Application specific compiler/architecture codesign: a case study
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Readings in hardware/software co-design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Design Tools for Application Specific Embedded Processors
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Instruction encoding synthesis for architecture exploration using hierarchical processor models
Proceedings of the 40th annual Design Automation Conference
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation
Proceedings of the 40th annual Design Automation Conference
Automated synthesis of efficient binary decoders for retargetable software toolkits
Proceedings of the 40th annual Design Automation Conference
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
High Level Synthesis from Sim-nML Processor Models
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Automatic Architectural Synthesis of VLIW and EPIC Processors
Proceedings of the 12th international symposium on System synthesis
RTGEN: An Algorithm for Automatic Generation of Reservation Tables from Architectural Descriptions
Proceedings of the 12th international symposium on System synthesis
Using Graph Models in Retargetable Optimizing Compilers for Microprocessors with VLIW Architectures
Cybernetics and Systems Analysis
An efficient retargetable framework for instruction-set simulation
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Techniques for accurate performance evaluation in architecture exploration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
RTGEN: an algorithm for automatic generation of reservation tables from architectural descriptions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
RTL Processor Synthesis for Architecture Exploration and Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Modeling and validation of pipeline specifications
ACM Transactions on Embedded Computing Systems (TECS)
Processor-memory coexploration using an architecture description language
ACM Transactions on Embedded Computing Systems (TECS)
Modular scheduling of guarded atomic actions
Proceedings of the 41st annual Design Automation Conference
A novel approach for flexible and consistent ADL-driven ASIP design
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Processor/Memory Co-Exploration on Multiple Abstraction Levels
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
The Journal of Supercomputing
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
DynamoSim: a trace-based dynamically compiled instruction set simulator
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Automatic generation of operation tables for fast exploration of bypasses in embedded processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting
Journal of VLSI Signal Processing Systems
Proceedings of the 41st annual Design Automation Conference
The ArchC architecture description language and tools
International Journal of Parallel Programming
A retargetable framework for instruction-set architecture simulation
ACM Transactions on Embedded Computing Systems (TECS)
Teaching computer architecture using an architecture description language
WCAE '04 Proceedings of the 2004 workshop on Computer architecture education: held in conjunction with the 31st International Symposium on Computer Architecture
An open-source binary utility generator
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2007 Summer Computer Simulation Conference
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
Journal of Signal Processing Systems
Processor Description Languages
Processor Description Languages
Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation
ACM Transactions on Embedded Computing Systems (TECS)
Proceedings of the 2nd International Conference on Simulation Tools and Techniques
MMV: a metamodeling based microprocessor validation environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Generic Instruction Set Simulator API for Timed and Untimed Simulation and Debug of MP2-SoCs
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
Orthogonal parallel processing in vector Pascal
Computer Languages, Systems and Structures
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
CGADL: an architecture description language for coarse-grained reconfigurable arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic generation of memory interfaces
SOC'09 Proceedings of the 11th international conference on System-on-chip
Versatile system-level memory-aware platform description approach for embedded MPSoCs
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
A model-driven automatically-retargetable debug tool for embedded systems
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Journal of Real-Time Image Processing
CIS'04 Proceedings of the First international conference on Computational and Information Science
Compiler analysis and supports for leakage power reduction on microprocessors
LCPC'02 Proceedings of the 15th international conference on Languages and Compilers for Parallel Computing
Compiler optimizations with DSP-Specific semantic descriptions
LCPC'02 Proceedings of the 15th international conference on Languages and Compilers for Parallel Computing
Automatic ADL-based assembler generation for ASIP programming support
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
A flexible approach to automated development of cross toolkits for embedded systems
PSI'09 Proceedings of the 7th international Andrei Ershov Memorial conference on Perspectives of Systems Informatics
Compiler backend generation for application specific instruction set processors
APLAS'11 Proceedings of the 9th Asian conference on Programming Languages and Systems
Journal of Systems Architecture: the EUROMICRO Journal
Bridging the chasm between MDE and the world of compilation
Software and Systems Modeling (SoSyM)
Automatic Generation of Memory Interfaces for ASIPs
International Journal of Embedded and Real-Time Communication Systems
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We present the Instruction Set Description Language,ISDL, a machine description language used to describetarget architectures to a retargetable compiler. The featuresand flexibility of ISDL enable the description of vastly differentarchitectures, in particular VLIW architectures. ISDL explicitlysupports constraints that define valid operation groupingswithin an instruction, increasing the range of specifiable architectures.We have written a tool that, given an ISDL descriptionof a processor, automatically generates an assembler forit. Ongoing work includes the development of an automaticcode-generator generator.