RTGEN: an algorithm for automatic generation of reservation tables from architectural descriptions

  • Authors:

  • Peter Grun;Ashok Halambi;Nikil Dutt;Alex Nicolau

  • Affiliations:

  • Architectures and Compilers for Embedded Systems (ACES) Laboratory, Center for Embedded Computer Systems, University of California at Irvine, Irvine, CA;Architectures and Compilers for Embedded Systems (ACES) Laboratory, Center for Embedded Computer Systems, University of California at Irvine, Irvine, CA;Architectures and Compilers for Embedded Systems (ACES) Laboratory, Center for Embedded Computer Systems, University of California at Irvine, Irvine, CA;Architectures and Compilers for Embedded Systems (ACES) Laboratory, Center for Embedded Computer Systems, University of California at Irvine, Irvine, CA

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Year:
  • 2003

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Abstract

Reservation Tables (RTs) have long been used to detect conflicts between operations that simultaneously access the same architectural resource. Traditionally, these RTs have been specified explicitly by the designer. However, the increasing complexity of modern processors makes the manual specification of RTs cumbersome and error prone. Furthermore, manual specification of such conflict information is infeasible for supporting rapid architectural exploration. In this paper, we present an algorithm to automatically generate RTs from a high-level processor description with the goal of avoiding manual specification of RTs, resulting in more concise architectural specifications and also supporting faster turn-around time in design space exploration. We demonstrate the utility of our approach on a set of experiments using the TI C6201 very long instruction Word digital signal processor and DLX processor architectures, and a suite of multimedia and scientific applications.