Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Artificial intelligence (2nd ed.)
Artificial intelligence (2nd ed.)
IMPACT: an architectural framework for multiple-instruction-issue processors
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
COMPCON '92 Proceedings of the thirty-seventh international conference on COMPCON
Compiler code transformations for superscalar-based high performance systems
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
The multiflow trace scheduling compiler
The Journal of Supercomputing - Special issue on instruction-level parallelism
The Journal of Supercomputing - Special issue on instruction-level parallelism
Detecting pipeline structural hazards quickly
POPL '94 Proceedings of the 21st ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Height reduction of control recurrences for ILP processors
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Iterative modulo scheduling: an algorithm for software pipelining loops
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Dynamic memory disambiguation using the memory conflict buffer
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
A reduced multipipeline machine description that preserves scheduling constraints
PLDI '96 Proceedings of the ACM SIGPLAN 1996 conference on Programming language design and implementation
Employing finite automata for resource scheduling
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
Efficient instruction scheduling using finite state automata
International Journal of Parallel Programming - Special issue on instruction-level parallel processing—part I
Exploiting instruction level parallelism in the presence of conditional branches
Exploiting instruction level parallelism in the presence of conditional branches
The Architecture of Symbolic Computers
The Architecture of Symbolic Computers
Developing the AMD-K5 Architecture
IEEE Micro
A representation for the analysis of microprogram operation
MICRO 7 Conference record of the 7th annual workshop on Microprogramming
A Control Word Model for detecting conflicts between microprograms
MICRO 8 Proceedings of the 8th annual workshop on Microprogramming
The optimization of horizontal microcode within and beyond basic blocks: an application of processor scheduling with resources
An efficient framework for performing execution-constraint-sensitive transformations that increase instruction-level parallelism
RTGEN: an algorithm for automatic generation of reservation tables from architectural descriptions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A machine description facility allows compiler writers to specify machine execution constraints to the optimization and scheduling phases of an instructionlevel parallelism (ILP) optimizing compiler. The machine description (MDES) facility should support quick development and easy maintenance of machine execution constraint descriptions by compiler writers. However, the facility should also allow compact representation and efficient usage of the MDES during compilation. This paper advocates a model that allows compiler writers to develop the MDES in a high-level language, which is then translated into a low-level representation for efficient use by the compiler. The discrepancy between the requirements of the high-level language and the low-level representation is reconciled with a collection of transformations that derive efficient lowlevel representations from the easy-to-understand high-level descriptions. In order to support these transformations, a novel approach to representing machine execution constraints has been developed. Detailed and precise descriptions of the execution constraints for the HP PA7100, Intel Pentium, SUN SuperSPARC, and AMD-K5 processors, as well as two hypothetical wider-issue processor configurations, are analyzed to show the advantage of using this new representation. The results show that performing these transformations and utilizing the new representation allow easy-to-maintain detailed descriptions written in high-level languages to be efficiently used by ILP-optimizing compilers.