A reduced multipipeline machine description that preserves scheduling constraints

  • Authors:

  • Alexandre E. Eichenberger;Edward S. Davidson

  • Affiliations:

  • Advanced Computer Architecture Laboratory, EECS Department, University of Michigan, 1301 Beal Ave, Ann Arbor, MI;Advanced Computer Architecture Laboratory, EECS Department, University of Michigan, 1301 Beal Ave, Ann Arbor, MI

  • Venue:
  • PLDI '96 Proceedings of the ACM SIGPLAN 1996 conference on Programming language design and implementation
  • Year:
  • 1996

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Abstract

High performance compilers increasingly rely on accurate modeling of the machine resources to efficiently exploit the instruction level parallelism of an application. In this paper, we propose a reduced machine description that results in faster detection of resource contentions while preserving the scheduling constraints present in the original machine description. The proposed approach reduces a machine description in an automated, error-free, and efficient fashion, Moreover, it fully supports schedulers that backtrack and process operations in arbitrary order. Reduced descriptions for the DEC Alpha 21064, MIPS R3000/R3010, and Cydra 5 result in 4 to 7 times faster detection of resource contentions and require 22 to 90% of the memory storage used by the original machine descriptions. Precise measurement for the Cydra 5 indicates that reducing the machine description results in a 2.9 times faster contention query module.