The multiflow trace scheduling compiler
The Journal of Supercomputing - Special issue on instruction-level parallelism
Detecting pipeline structural hazards quickly
POPL '94 Proceedings of the 21st ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Iterative modulo scheduling: an algorithm for software pipelining loops
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
A reduced multipipeline machine description that preserves scheduling constraints
PLDI '96 Proceedings of the ACM SIGPLAN 1996 conference on Programming language design and implementation
Efficient instruction scheduling using finite state automata
International Journal of Parallel Programming - Special issue on instruction-level parallel processing—part I
ISDL: an instruction set description language for retargetability
DAC '97 Proceedings of the 34th annual Design Automation Conference
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Advanced compiler design and implementation
Advanced compiler design and implementation
A processor desription language supporting retargetable multi-pipeline DSP program development tools
Proceedings of the 11th international symposium on System synthesis
Optimization of machine descriptions for efficient use
International Journal of Parallel Programming - Special issue: MICRO-29, 29th annual IEEE/ACM international symposium on microarchitecture
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Memory aware compilation through accurate timing extraction
Proceedings of the 37th Annual Design Automation Conference
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Architecture exploration of parameterizable EPIC SOS architectures (poster paper)
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Access pattern based local memory customization for low power embedded systems
Proceedings of the conference on Design, automation and test in Europe
Quick piping: a fast, high-level model for describing processor pipelines
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
MIST: an algorithm for memory miss traffic management
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Instruction Scheduler Generation for Retargetable Compilation
IEEE Design & Test
Pipeline Modeling for Timing Analysis
SAS '02 Proceedings of the 9th International Symposium on Static Analysis
Processor-memory coexploration using an architecture description language
ACM Transactions on Embedded Computing Systems (TECS)
A procedure for obtaining a behavioral description for the control logic of a non-linear pipeline
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Retargetable pipeline hazard detection for partially bypassed processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Reservation Tables (RTs) have long been used to detect conflicts between operations that simultaneously access the same architectural resource. Traditionally, these RTs have been specified explicitly by the designer. However, the increasing complexity of modern processors makes the manual specification of RTs cumbersome and error-prone. Furthermore, manual specification of such conflict information is infeasible for supporting rapid architectural exploration. In this paper we present an algorithm to automatically generate RTs from a high-level processor description, with the goal of avoiding manual specification of RTs, resulting in more concise architectural specifications and also supporting faster turn-around time in Design Space Exploration. We demonstrate the utility of our approach on a set of experiments using the TI C6201 VLIW DSP and DLX processor architectures, and a suite of multimedia and scientific applications.