Reasoning About Time in Higher-Level Language Software
IEEE Transactions on Software Engineering
Calculating the maximum, execution time of real-time programs
Real-Time Systems
The Marion system for retargetable instruction scheduling
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
A processor desription language supporting retargetable multi-pipeline DSP program development tools
Proceedings of the 11th international symposium on System synthesis
Bounding Pipeline and Instruction Cache Performance
IEEE Transactions on Computers
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Pipeline behavior prediction for superscalar processors by abstract interpretation
Proceedings of the ACM SIGPLAN 1999 workshop on Languages, compilers, and tools for embedded systems
Worst Case Execution Time Analysis for a Processor withBranch Prediction
Real-Time Systems - Special issue on worst-case execution-time analysis
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
An Accurate Worst Case Timing Analysis for RISC Processors
IEEE Transactions on Software Engineering
Reliable and Precise WCET Determination for a Real-Life Processor
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques
LCTES '98 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Generation of Efficient Interprocedural Analyzers with PAG
SAS '95 Proceedings of the Second International Symposium on Static Analysis
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RTCSA '00 Proceedings of the Seventh International Conference on Real-Time Systems and Applications
Worst case timing analysis of RISC processors: R3000/R3010 case study
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Integrating the timing analysis of pipelining and instruction caching
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Cache modeling for real-time software: beyond direct mapped instruction caches
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Combining Abstract Interpretation and ILP for Microarchitecture Modelling and Program Path Analysis
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
RTGEN: An Algorithm for Automatic Generation of Reservation Tables from Architectural Descriptions
Proceedings of the 12th international symposium on System synthesis
Modeling out-of-order processors for WCET analysis
Real-Time Systems
Towards formally verifiable resource bounds for real-time embedded systems
ACM SIGBED Review - Special issues on workshop on innovative techniques for certification of embedded systems
Proceedings of the 2007 ACM symposium on Applied computing
WCET analysis of instruction caches with prefetching
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Timing predictability of cache replacement policies
Real-Time Systems
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Analyzing the worst-case execution time for instruction caches with prefetching
ACM Transactions on Embedded Computing Systems (TECS)
Towards a Statistical Model of a Microprocessor's Throughput by Analyzing Pipeline Stalls
SEUS '09 Proceedings of the 7th IFIP WG 10.2 International Workshop on Software Technologies for Embedded and Ubiquitous Systems
Worst-case execution times for a purely functional language
IFL'06 Proceedings of the 18th international conference on Implementation and application of functional languages
100% coverage for safety-critical software - efficient testing by static analysis
SAFECOMP'10 Proceedings of the 29th international conference on Computer safety, reliability, and security
On abstractions for timing analysis in the K framework
FOPARA'11 Proceedings of the Second international conference on Foundational and Practical Aspects of Resource Analysis
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In hard real-time systems, the worst-case execution times of programs must be known. Obtaining safe upper bounds for these times by measuring actual executions is rarely possible, since the worst case input is normally not known. We apply static program analysis methods to determine an upper bound for the WCET. While this approach is not new, we believe to be the first to have developed a tool that implements these techniques for all the features of a real-life, non-trivial processor, the Motorola ColdFire 5307. Our tool is, to the best of our knowledge, the first one that can determine a safe and rather precise WCET bound for a processor that has caches and pipelines and performs branch prediction and instruction prefetching.Our approach to use a pipeline model in the analysis of the processor behavior opens up new perspectives towards a generative analysis approach and can prove helpful in investigating other processor properties. The emphasis of this paper is on the modeling of the pipeline behavior as input to the derivation of a pipeline analysis.