The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
Retargetable instruction scheduling for pipelined processors
Retargetable instruction scheduling for pipelined processors
Optimally profiling and tracing programs
POPL '92 Proceedings of the 19th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
An Accurate Worst Case Timing Analysis for RISC Processors
IEEE Transactions on Software Engineering
On Predicting Data Cache Behavior for Real-Time Systems
LCTES '98 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques
LCTES '98 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
CC '98 Proceedings of the 7th International Conference on Compiler Construction
Worst case timing analysis of RISC processors: R3000/R3010 case study
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Efficient microarchitecture modeling and path analysis for real-time software
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Integrating the timing analysis of pipelining and instruction caching
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Combining Abstract Interpretation and ILP for Microarchitecture Modelling and Program Path Analysis
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
A Worst Case Timing Analysis Technique for Multiple-Issue Machines
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
Fast and Precise WCET Prediction by Separated Cache andPath Analyses
Real-Time Systems - Special issue on worst-case execution-time analysis
WCET Analysis of Superscalar Processors Using SimulationWith Coloured Petri Nets
Real-Time Systems - Special issue on worst-case execution-time analysis
Efficient longest executable path search for programs with complex flows and pipeline effects
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Timing analysis of embedded software for speculative processors
Proceedings of the 15th international symposium on System Synthesis
Processor Pipelines and Their Properties for Static WCET Analysis
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
ILP-Based Interprocedural Path Analysis
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Pipeline Modeling for Timing Analysis
SAS '02 Proceedings of the 9th International Symposium on Static Analysis
Clustered calculation of worst-case execution times
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Modeling control speculation for timing analysis
Real-Time Systems
Clustered Worst-Case Execution-Time Calculation
IEEE Transactions on Computers
Modeling out-of-order processors for WCET analysis
Real-Time Systems
Proceedings of the conference on Design, automation and test in Europe
Towards Model-Driven Development of Hard Real-Time Systems
Model-Driven Development of Reliable Automotive Services
WCET Analysis of Data Dependent, Component Oriented, Embedded Software Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
100% coverage for safety-critical software - efficient testing by static analysis
SAFECOMP'10 Proceedings of the 29th international conference on Computer safety, reliability, and security
Modeling complex flows for worst-case execution time analysis
RTSS'10 Proceedings of the 21st IEEE conference on Real-time systems symposium
Cache and pipeline sensitive fixed priority scheduling for preemptive real-time systems
RTSS'10 Proceedings of the 21st IEEE conference on Real-time systems symposium
A functional approach to worst-case execution time analysis
WFLP'11 Proceedings of the 20th international conference on Functional and constraint logic programming
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For real time systems not only the logical function is important but also the timing behavior, e. g. hard real time systems must react inside their deadlines. To guarantee this it is necessary to know upper bounds for the worst case execution times (WCETs). The accuracy of the prediction of WCETs depends strongly on the ability to model the features of the target processor.Cache memories, pipelines and parallel functional units are architectural components which are responsible for the speed gain of modern processors. It is not trivial to determine their influence when predicting the worst case execution time of programs.This paper describes a method to predict the behavior of pipelined superscalar processors and reports initial results of a prototypical implementation for the SuperSPARC I processor.