Static timing analysis of embedded software
DAC '97 Proceedings of the 34th annual Design Automation Conference
Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemptive Scheduling
IEEE Transactions on Computers
Bounding Pipeline and Instruction Cache Performance
IEEE Transactions on Computers
Pipeline behavior prediction for superscalar processors by abstract interpretation
Proceedings of the ACM SIGPLAN 1999 workshop on Languages, compilers, and tools for embedded systems
Timing Analysis for Data and Wrap-Around Fill Caches
Real-Time Systems
Cache-Conscious Limited Preemptive Scheduling
Real-Time Systems
Guest Editorial: A Review of Worst-Case Execution-TimeAnalysis
Real-Time Systems - Special issue on worst-case execution-time analysis
Supporting Timing Analysis by Automatic Bounding of LoopIterations
Real-Time Systems - Special issue on worst-case execution-time analysis
Symbolic Cache Analysis for Real-Time Systems
Real-Time Systems - Special issue on worst-case execution-time analysis
Timing Analysis for Instruction Caches
Real-Time Systems - Special issue on worst-case execution-time analysis
Worst Case Execution Time Analysis for a Processor withBranch Prediction
Real-Time Systems - Special issue on worst-case execution-time analysis
WCET Analysis of Superscalar Processors Using SimulationWith Coloured Petri Nets
Real-Time Systems - Special issue on worst-case execution-time analysis
Low-energy intra-task voltage scheduling using static timing analysis
Proceedings of the 38th annual Design Automation Conference
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Hardware compilation of sequential ada
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Energy-conserving feedback EDF scheduling for embedded systems with real-time constraints
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Hardware implementation of the Ravenscar Ada tasking profile
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Data-Flow Frameworks for Worst-Case Execution Time Analysis
Real-Time Systems
Intra-Task Voltage Scheduling for Low-Energy, Hard Real-Time Applications
IEEE Design & Test
Automatic detection and exploitation of branch constraints for timing analysis
IEEE Transactions on Software Engineering
Language Issues of Compiling Ada to Hardware
Ada-Europe '02 Proceedings of the 7th Ada-Europe International Conference on Reliable Software Technologies
Pipeline Modeling for Timing Analysis
SAS '02 Proceedings of the 9th International Symposium on Static Analysis
Timing Analysis of Assembler Code Control-Flow Paths
FME '02 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods - Getting IT Right
Data cache locking for higher program predictability
SIGMETRICS '03 Proceedings of the 2003 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Virtual simple architecture (VISA): exceeding the complexity limit in safe real-time systems
Proceedings of the 30th annual international symposium on Computer architecture
FAST: Frequency-Aware Static Timing Analysis
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Data Caches in Multitasking Hard Real-Time Systems
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Compositional static instruction cache simulation
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Safely exploiting multithreaded processors to tolerate memory latency in real-time systems
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Improving WCET by applying a WC code-positioning optimization
ACM Transactions on Architecture and Code Optimization (TACO)
FAST: Frequency-aware static timing analysis
ACM Transactions on Embedded Computing Systems (TECS)
Improving WCET by applying worst-case path optimizations
Real-Time Systems
WCET analysis of instruction caches with prefetching
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Bump-pointer method caching for embedded Java processors
JTRES '07 Proceedings of the 5th international workshop on Java technologies for real-time and embedded systems
Data cache locking for tight timing calculations
ACM Transactions on Embedded Computing Systems (TECS)
A time-predictable VLIW processor and its compiler support
Real-Time Systems
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Analyzing the worst-case execution time for instruction caches with prefetching
ACM Transactions on Embedded Computing Systems (TECS)
Exploiting stack distance to estimate worst-case data cache performance
Proceedings of the 2009 ACM symposium on Applied Computing
Time-predictable computer architecture
EURASIP Journal on Embedded Systems - FPGA supercomputing platforms, architectures, and techniques for accelerating computationally complex algorithms
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Delivering real-time behaviour
Domain modeling and the duration calculus
Worst-case execution time analysis for a Java processor
Software—Practice & Experience
Parametric timing analysis and its application to dynamic voltage scaling
ACM Transactions on Embedded Computing Systems (TECS)
Cache persistence analysis: a novel approachtheory and practice
Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Stack distance based worst-case instruction cache performance analysis
Proceedings of the 2011 ACM Symposium on Applied Computing
Journal of Systems Architecture: the EUROMICRO Journal
A Model Checking Based Approach to Bounding Worst-Case Execution Time for Multicore Processors
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on CAPA'09, Special Section on WHS'09, and Special Section VCPSS' 09
Data cache organization for accurate timing analysis
Real-Time Systems
Cache persistence analysis: Theory and practice
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
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Recently designed machines contain pipelines and caches. While both features provide significant performance advantages, they also pose problems for predicting execution time of code segments in real-time systems. Pipeline hazards may result in multicycle delays. Instruction or data memory references may not be found in cache and these misses typically require several cycles to resolve. Whether an instruction will stall due to a pipeline hazard or a cache miss depends on the dynamic sequence of previous instructions executed and memory references performed. Furthermore, these penalties are not independent since delays due to pipeline stalls and cache miss penalties may overlap. This paper describes an approach for bounding the worst-case performance of large code segments on machines that exploit both pipelining and instruction caching. First, a method is used to analyze a program's control flow to statically categorize the caching behavior of each instruction. Next, these categorizations are used in the pipeline analysis of sequences of instructions representing paths within the program. A timing analyzer uses the pipeline path analysis to estimate the worst-case execution performance of each loop and function in the program. Finally, a graphical user interface is invoked that allows a user to request timing predictions on portions of the program.