Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems

  • Authors:

  • Reinhard Wilhelm;Daniel Grund;Jan Reineke;Marc Schlickling;Markus Pister;Christian Ferdinand

  • Affiliations:

  • Saarland University, Saarbrücken, Germany and Leibniz Center for Computer Science, Schloss Dagstuhl, Saarland, Germany;Saarland University, Saarbrücken, Germany;Saarland University, Saarbrücken, Germany;Saarland University, Saarbrücken, Germany and AbsInt Angewandte Informatik GmbH, Saarbrücken, Germany;Saarland University, Saarbrücken, Germany and AbsInt Angewandte Informatik GmbH, Saarbrücken, Germany;AbsInt Angewandte Informatik GmbH

  • Venue:
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • Year:
  • 2009

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Abstract

Embedded hard real-time systems need reliable guarantees for the satisfaction of their timing constraints. Experience with the use of static timing-analysis methods and the tools based on them in the automotive and the aeronautics industries is positive. However, both the precision of the results and the efficiency of the analysis methods are highly dependent on the predictability of the execution platform. In fact, the architecture determines whether a static timing analysis is practically feasible at all and whether the most precise obtainable results are precise enough. Results contained in this paper also show that measurement-based methods still used in industry are not useful for quite commonly used complex processors. This dependence on the architectural development is of growing concern to the developers of timing-analysis tools and their customers, the developers in industry. The problem reaches a new level of severity with the advent of multicore architectures in the embedded domain. This paper describes the architectural influence on static timing analysis and gives recommendations as to profitable and unacceptable architectural features.