Amortized efficiency of list update and paging rules
Communications of the ACM
Performance analysis of embedded software using implicit path enumeration
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient and Precise Cache Behavior Prediction for Real-TimeSystems
Real-Time Systems
Supporting Timing Analysis by Automatic Bounding of LoopIterations
Real-Time Systems - Special issue on worst-case execution-time analysis
Worst Case Execution Time Analysis for a Processor withBranch Prediction
Real-Time Systems - Special issue on worst-case execution-time analysis
An anomaly in space-time characteristics of certain programs running in a paging machine
Communications of the ACM
Automatic discovery of linear restraints among variables of a program
POPL '78 Proceedings of the 5th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Deriving Annotations for Tight Calculation of Execution Time
Euro-Par '97 Proceedings of the Third International Euro-Par Conference on Parallel Processing
Reliable and Precise WCET Determination for a Real-Life Processor
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
ILP-Based Interprocedural Path Analysis
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Timing Analysis for Data Caches and Set-Associative Caches
RTAS '97 Proceedings of the 3rd IEEE Real-Time Technology and Applications Symposium (RTAS '97)
Cache modeling for real-time software: beyond direct mapped instruction caches
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Timing Anomalies in Dynamically Scheduled Microprocessors
RTSS '99 Proceedings of the 20th IEEE Real-Time Systems Symposium
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
Worst-Case Execution Time Analysis for Dynamic Branch Predictors
ECRTS '04 Proceedings of the 16th Euromicro Conference on Real-Time Systems
Design for Timing Predictability
Real-Time Systems
Modeling control speculation for timing analysis
Real-Time Systems
A WCET-Oriented Static Branch Prediction Scheme for Real Time Systems
ECRTS '05 Proceedings of the 17th Euromicro Conference on Real-Time Systems
A Case for Static Branch Prediction in Real-Time Systems
RTCSA '05 Proceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
The case for the precision timed (PRET) machine
Proceedings of the 44th annual Design Automation Conference
Timing predictability of cache replacement policies
Real-Time Systems
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Relative competitive analysis of cache replacement policies
Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems
Abstract Interpretation of FIFO Replacement
SAS '09 Proceedings of the 16th International Symposium on Static Analysis
Evaluation techniques for storage hierarchies
IBM Systems Journal
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Precise and Efficient FIFO-Replacement Analysis Based on Static Phase Detection
ECRTS '10 Proceedings of the 2010 22nd Euromicro Conference on Real-Time Systems
Computation takes time, but how much?
Communications of the ACM
A Unified WCET analysis framework for multicore platforms
ACM Transactions on Embedded Computing Systems (TECS)
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One step in the verification of hard real-time systems is to determine upper bounds on the worst-case execution times (WCET) of tasks. To obtain tight bounds, a WCET analysis has to consider micro-architectural features like caches, branch prediction, and branch target buffers (BTB). We propose a modular WCET analysis framework for branch target buffers, which allows for easy adaptability to different BTBs. As an example, we investigate the Motorola PowerPC 56x family (MPC56x), which is used in automotive and avionic systems. On a set of avionic and compiler benchmarks, our analysis improves WCET bounds on average by 17% over no BTB analysis. Capitalizing on the modularity of our framework, we explore alternative hardware designs. We propose more predictable designs, which improve obtainable WCET bounds by up to 20%, reduce analysis time considerably, and simplify the analysis. We generalize our findings and give advice concerning hardware used in real-time systems.